Display Data Receiving Circuit with Adjustable Clock Frequency
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Solution Overview
Problem
Existing liquid crystal display apparatuses face challenges in reducing power consumption, particularly in the display data receiving circuit, where power consumption is not effectively minimized during data transfer, and design optimizations for high transfer rates unnecessarily increase power consumption at slow rates.
Innovation Solution
A display data receiving circuit with clock regeneration circuits generating internal clock signals at adjustable frequencies and a serial/parallel conversion circuit capable of single or double edge operations, optimizing power usage based on transfer rates by switching between high-frequency single edge operation for fast data transfer and low-frequency double edge operation for slow data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the display data receiving circuit is designed to receive display data at high transfer rates, then data transfer reliability is improved, but power consumption increases unnecessarily at slow transfer rates
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable based on operating conditions. The clock regeneration circuit can generate internal clock signals at different frequencies (e.g., first frequency for high-speed mode, second frequency for low-power mode), allowing the system to adapt its clock frequency to match the actual data transfer rate requirements, thus avoiding unnecessary power consumption at slow transfer rates while maintaining reliability at high rates
Solution Approach 2:
The patent changes the parameter of clock frequency dynamically. By switching between different clock frequencies (first frequency vs. second frequency) based on whether high-speed reception is needed, the system optimizes the balance between data transfer reliability and power consumption. The serial/parallel conversion circuit also switches between single-edge and double-edge operations corresponding to different frequency modes
2Speed
If the clock frequency is increased to achieve high data transfer rates, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts clock frequency based on display panel resolution and data transfer requirements. For high-resolution panels (e.g., XGA) requiring fast transfer, the clock operates at first frequency. For low-resolution panels (e.g., QVGA) with slower transfer needs, the clock switches to second frequency, reducing power consumption while maintaining adequate transfer speed
Solution Approach 2:
The patent changes the clock frequency parameter from fixed to variable. The clock regeneration circuit generates internal clock signals at different frequencies depending on the operating mode, directly controlling the data transfer rate and associated power consumption. This parameter change is coordinated with the serial/parallel conversion circuit's edge operation mode
3Use of energy by moving object
If the display data receiving circuit operates in single edge operation mode, then power consumption is reduced, but data transfer reliability decreases at high transfer rates
Solution Approach 1:
The patent dynamically switches between single-edge and double-edge operation modes in the serial/parallel conversion circuit based on the clock frequency and data transfer rate. At high frequencies where reliability is critical, double-edge operation is used to ensure accurate data reception. At low frequencies where power consumption is prioritized, single-edge operation suffices, maintaining reliability while reducing power usage
Data Source
AI summary
A display data receiving circuit of the present invention includes a PLL circuit 25 which generates internal clock signal ICLK having an integral multiple of the frequency of differential clock signals CLK and /CLK in response to differential clock signals CLK and /CLK, and a serial/parallel conversion circuit 23 which receives serial data signal transmitting display data in synchronization with the internal clock signal ICLK, and generates parallel data signal by executing serial/parallel conversion for the serial data signal. The serial/parallel conversion circuit 23 is configured to be able to execute either a single edge operation, which receives serial data signals in response to one of a rising edge and a falling edge of the internal clock signal ICLK, or a double edge operation, which receives serial data signals in response to both of a rising edge and a falling edge of the internal clock signal ICLK. Further, the PLL circuit 25 is configured to be able to change the frequency of the internal clock signal ICLK.