Display Device Data Signal Output Timing Control
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Solution Overview
Problem
In display devices, the uncontrolled output timing of data signals between data driving circuit units leads to varying pixel charging times, resulting in luminance differences across the display panel.
Innovation Solution
A display device with a signal controller and data driver that includes clock adjustment units generating second clock signals using a first clock signal and frame control signal, ensuring synchronized output timing across data line groups, and utilizing clock shifters and latch units to control data signal transmission to each channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data signals are output without controlling output timing between data driving circuit units, then the device complexity is reduced, but luminance uniformity deteriorates due to varying pixel charging times
Solution Approach 1:
The patent changes the timing parameter of data signal output by introducing a delay time that varies across data driving circuit units. Specifically, the n-th data driving circuit unit delays the output timing by (n-1)×K clock cycles, where K is a predetermined value. This parameter change synchronizes pixel charging times across different data line groups, eliminating luminance differences while maintaining system simplicity
Solution Approach 2:
The patent applies preliminary action by pre-calculating and pre-setting the delay time for each data driving circuit unit based on its position (n-th unit). The delay amount is determined in advance as (n-1)×K clock cycles, allowing the system to compensate for timing differences before they affect pixel charging, thereby ensuring luminance uniformity without complex real-time control
2Stability of the object's composition
If output timing of data signal is controlled using clock adjustment units, then luminance uniformity is improved, but device complexity increases
Solution Approach 1:
The patent segments the timing control function by assigning independent clock adjustment units to each data driving circuit unit. Each unit independently generates delayed clock signals according to its position, with the n-th unit applying (n-1)×K clock cycle delays. This segmentation allows distributed timing control that achieves luminance uniformity without requiring a complex centralized control system
Solution Approach 2:
The patent applies local quality by making each data driving circuit unit have a specific delay characteristic tailored to its position. The n-th unit has a delay of (n-1)×K clock cycles, creating a gradient of delay times across the system. This local differentiation in timing parameters compensates for position-dependent variations in pixel charging, achieving luminance uniformity through localized adjustments
Data Source
AI summary
A display device includes a signal controller configured to provide data and a frame control signal, a display panel including first to m-th data line groups, and a data driver configured to receive the data and the frame control signal, and output a data signal corresponding to the data to the first to m-th data line groups. The data driver includes first to m-th data driving circuit units electrically connected to the first to m-th data line groups in one-to-one correspondence, Each of the first to m-th data driving circuit units includes a clock adjustment unit configured to generate a second clock signal using a first clock signal and the frame control signal. The second clock signal controls an output timing of the data signal to be transmitted to a first channel among a plurality of channels of each of the first to m-th data line groups.