Display Decoder Circuit Using Cascode Differential Pairs
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Solution Overview
Problem
Existing display device decoder circuits face challenges in miniaturization and yield due to the need for multiple current sources, which increase chip area and complexity, especially when dealing with large differences in input voltages.
Innovation Solution
A multiple-input single-output circuit using a cascode transistor section with a constant current source and differential pairs to generate an intermediate output voltage without subdividing current sources, allowing for accurate voltage output from multiple input voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two constant current sources are used to eliminate voltage shift, then voltage output accuracy is improved, but circuit area increases and manufacturing difficulty increases
Solution Approach 1:
The patent merges multiple current sources into a single current source by using a current mirror circuit. The first and second constant current sources are combined through the current mirror transistor section, allowing one physical current source to provide the function of multiple current sources. This reduces the circuit area while maintaining the ability to generate accurate intermediate voltages.
Solution Approach 2:
The single current source in the patent serves multiple functions simultaneously. It provides bias current for the differential pairs and works in conjunction with the current mirror circuit to generate multiple effective current paths. This multi-functionality allows the circuit to achieve the voltage accuracy previously requiring multiple separate current sources.
2Area of stationary object
If gate width is made narrower to reduce circuit area, then area is reduced, but manufacturing yield deteriorates
Solution Approach 1:
By merging multiple current sources into one through the current mirror configuration, the patent reduces the total transistor count and circuit area. This allows transistors to maintain adequate gate widths for good manufacturing yield while achieving compact circuit design.
Solution Approach 2:
The patent segments the current source function across multiple transistors in the current mirror circuit rather than requiring a single large current source. This segmentation allows each transistor to have reasonable dimensions for manufacturing while collectively providing the required current characteristics.
3Adaptability or versatility
If decoder circuit scale is increased to handle more gray-scale levels, then gray-scale capability is improved, but chip area increases
Solution Approach 1:
The current mirror circuit merges multiple current source functions into a compact configuration that supports multiple gray-scale levels. This allows the decoder to handle increased gray-scale capability without proportionally increasing the chip area, as the current generation circuitry is shared across multiple output levels.
Solution Approach 2:
The differential pair and current mirror configuration serves as a universal building block that can be reused for multiple gray-scale decoding functions. This multi-functionality allows the same circuit topology to support various gray-scale levels without requiring separate dedicated circuits for each level.
Data Source
AI summary
A circuit that obtains a more accurate, output voltage from a plurality of input voltages is provided. A two-input single-output circuit includes a current source transistor allowing a predetermined current to flow, a cascode transistor section including two MOS transistors that are cascode-connected to the drain side of the current source transistor and have the same characteristics, a differential pair section having a first differential pair formed of a first input-side transistor and a first output-side transistor whose source lines are shared and a second differential pair formed of a second input-side transistor and a second output-side transistor whose source lines are shared, and a current mirror circuit section. Drain lines of the transistors of the cascade transistor section are respectively connected to the source lines of the first and second differential pairs.