Display Demultiplexer Timing Layout for Lower EMI
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Solution Overview
Problem
Display devices face challenges in meeting electromagnetic interference (EMI) standards due to the complexity of reducing EMI in their design and operation.
Innovation Solution
The implementation of a display device with a control signal generator, demultiplexers, and signal delay parts that time-divide and distribute data voltages to multiple data lines, synchronized with delayed control signals, to create time differences in switch on/off timings of demultiplexers, thereby reducing EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple demultiplexers are used to distribute data voltages to multiple data lines, then the data distribution capability is improved, but the electromagnetic interference increases due to simultaneous switching
Solution Approach 1:
The patent applies periodic action by sequentially enabling different demultiplexers at different time periods. The control signal generator generates staggered control signals that activate demultiplexers in a sequential manner rather than simultaneously, thereby distributing data voltages over time while reducing electromagnetic interference caused by simultaneous switching operations.
Solution Approach 2:
The patent segments the simultaneous switching operation into multiple sequential switching operations. By dividing the data distribution task across multiple time slots with different demultiplexers active at different times, the system maintains high data distribution capability while reducing the peak electromagnetic interference that would occur with simultaneous switching.
2Productivity
If demultiplexers are switched on/off simultaneously to distribute data, then the data transmission efficiency is improved, but the EMI compliance becomes difficult to meet
Solution Approach 1:
The control signal generator implements periodic action by generating time-staggered control signals for different demultiplexers. This ensures that data transmission continues efficiently through sequential processing while each demultiplexer switches on and off at different times, thereby meeting EMI compliance requirements.
Solution Approach 2:
The control signal generator performs preliminary action by pre-coordinating the switching timings of multiple demultiplexers. By planning and executing staggered switching sequences in advance, the system optimizes data transmission efficiency while proactively preventing EMI issues before they occur.
3Stability of the object's composition
If the switching timings of demultiplexers are synchronized, then the data distribution coordination is improved, but the EMI is increased due to simultaneous switching operations
Solution Approach 1:
The patent applies periodic action by implementing a periodic staggered switching pattern. The control signal generator creates a stable, repeating sequence where demultiplexers switch on and off at regular, offset intervals. This maintains coordinated data distribution while avoiding the electromagnetic interference of simultaneous switching.
Solution Approach 2:
The patent applies asymmetry by deliberately creating asymmetric switching timings among demultiplexers. Instead of symmetric simultaneous switching, each demultiplexer operates at a different time offset, breaking the symmetry that causes EMI while maintaining overall coordination through the structured asymmetric pattern.
Data Source
AI summary
A display device and a method of driving the same are provided. The display device includes a control signal generator that generates a control signal, a first demultiplexer that time-divides a data voltage from a first channel of a data driver and distributes the data voltage from the first channel to two or more data lines, in response to the control signal, a signal delay part that delays the control signal, and a second demultiplexer that time-divides a data voltage from a second channel of the data driver and distributes the data voltage from the second channel to other two or more data lines, in response to the control signal delayed by the signal delay part.