Display device and electronic signboard

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Solution Overview

Problem

Conventional display devices, such as those using Memory-in-Pixel (MIP) technology, face challenges in achieving high definition due to power consumption issues with DRAM and large circuit scale of SRAM, making it difficult to reduce power consumption and achieve high definition displays.

Innovation Solution

The display device incorporates sub-pixels with memory blocks using first and second transistors with floating gates, where the drains of these transistors are coupled, and the sub-pixel electrode is connected to a node that stores data based on electrical charge, allowing for efficient data storage and display without the need for continuous power supply.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If DRAM is used as memory in each pixel, then the display device can be implemented with existing technology, but power consumption increases due to required refresh operations

Engineering Contradiction:
Improvememory functionalityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the fundamental parameter of memory type from volatile (DRAM) to non-volatile (floating gate transistor), eliminating the need for refresh operations and thereby reducing power consumption while maintaining data storage functionality in each pixel

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If SRAM is used as memory in each pixel, then power consumption can be reduced, but the circuit scale becomes large making high definition difficult

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit scale
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent changes the memory implementation from SRAM (requiring multiple transistors per bit) to a simplified floating gate transistor structure that stores data in the threshold voltage of a single transistor, dramatically reducing circuit scale while maintaining low power consumption characteristics

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts the memory function from complex multi-transistor SRAM circuits and implements it using only the threshold voltage characteristic of a single floating gate transistor, removing unnecessary circuit components while preserving the essential data storage capability

Inventive Principle:
Principle #2Taking out (Extraction)

3Use of energy by moving object

If floating gate transistors are used for memory storage, then power consumption is reduced and circuit scale is minimized, but data storage mechanism becomes more complex

Engineering Contradiction:
Improvepower consumptionVSAvoiddata storage mechanism
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The floating gate transistor uses its own threshold voltage characteristic to store data, requiring no external refresh circuits or additional control logic, thereby simplifying the overall system despite the specialized memory mechanism

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces power consumption, minimizes circuit complexity, and enables high-definition imaging by effectively storing and retrieving data in sub-pixels without continuous power, thus addressing the limitations of existing MIP technologies.

Implementation Method 1

first and second transistors configured to store therein sub-pixel data in accordance with an electrical charge of a floating gate

Methodology Applied
Scientific EffectElectrical charge storage in floating gate: Capacitance

Data Source

PatentUS11545102B2Display device and electronic signboard
Publication Date: 2023.01.03 MAGNOLIA WHITE CORP
  • US11545102B2 patent drawing
  • US11545102B2 patent drawing
  • US11545102B2 patent drawing

AI summary

According to an aspect, a display device includes a plurality of sub-pixels. Each of the sub-pixels includes a memory block including a memory configured to store therein sub-pixel data and a sub-pixel electrode coupled to the memory block. The memory includes first and second transistors configured to store therein the sub-pixel data in accordance with an electrical charge of a floating gate, the first and second transistors include respective drains that are coupled to each other, and a coupling point of the drains is coupled to a node. The sub-pixel electrode is coupled to the node, and each of the sub-pixels is configured to display an image based on a potential of the node.