Display Device Neural Network Bit Width Dynamics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices face challenges in reducing hardware size while performing neural network computations, leading to increased costs and power consumption due to the requirement of large multipliers, memories, and registers for artificial intelligence processing.
Innovation Solution
A method and display device that utilize a lightweight convolutional neural network with reduced bit width weights, performing neural network computations by determining a shift distance for input feature data, reducing its bit width, and performing convolution operations with restored bit width, thereby reducing hardware requirements and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional neural network computations are performed with full bit width, then computation accuracy is maintained, but hardware size and power consumption increase significantly
Solution Approach 1:
The patent applies dynamic bit width adjustment by determining shift distances based on the actual values of input feature data. The bit width is dynamically reduced during convolution operations and restored afterward, allowing the system to adapt computation precision to the specific data being processed rather than using a fixed high bit width throughout, thereby reducing hardware size while maintaining accuracy when needed
Solution Approach 2:
The patent changes the bit width parameter of the neural network weights and feature data during computation. By reducing the bit width from its original full precision to a reduced bit width for convolution operations, and then restoring it afterward, the system achieves lower hardware requirements while maintaining computation accuracy through selective parameter adjustment
2Measurement precision
If traditional neural network computations are performed with full bit width, then computation accuracy is maintained, but power consumption increases
Solution Approach 1:
The system dynamically adjusts bit width based on input feature data values, reducing computation precision only when appropriate and restoring it when needed. This dynamic approach reduces power consumption during convolution operations while maintaining accuracy requirements, as the bit width is adjusted rather than permanently reduced
Solution Approach 2:
By changing the bit width parameter during computation and restoring it afterward, the system reduces power consumption during the actual convolution operations without permanently compromising computation accuracy. The parameter change allows the system to use lower power modes when appropriate while maintaining high precision when required
3Ease of manufacture
If hardware size is reduced by using smaller multipliers and memories, then manufacturing cost decreases, but neural network computation capability is compromised
Solution Approach 1:
The patent enables smaller hardware components to perform full-capability neural network computations by dynamically adjusting bit width. The reduced bit width during convolution allows smaller multipliers and memories to be used, while the restoration of bit width afterward maintains the system's ability to handle full-precision requirements when needed, thus preserving computation capability despite reduced hardware size
Data Source
AI summary
A method of performing a convolution operation is provided. The method includes obtaining a lightweight convolutional neural network with a reduced bit width of weights, and inputting input data to the convolutional neural network and performing neural network computations to obtain output data. The neural network computations includes determining a shift distance based on a value of input feature data, performing a shift operation to reduce a bit width of the input feature data based on the shift distance, performing a convolution operation on the input feature data with the reduced bit width and the weights with the reduced bit width, wherein the convolution operation includes a shift operation of restoring the bit width, and obtaining output feature data with the restored bit width.