Display Device Bypass Line Layering for Wider Hole-Area Screens

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Solution Overview

Problem

The formation of holes in the display area of display devices to accommodate functional modules leads to non-display areas where wires are disposed adjacently, causing image disruption and reducing the usable screen size.

Innovation Solution

The implementation of bypass data and gate lines in alternate layers in the peripheral area, reducing coupling and allowing for a wider display area by spacing the lines apart, thereby maintaining image integrity around the hole.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wires are disposed in the display area adjacent to the hole edge to bypass the hole, then electrical connection is maintained, but image display quality deteriorates and non-display area increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidimage display quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies multi-layer stacking to route bypass lines through the third dimension (vertical layer structure) rather than confining them to the planar display area. By alternating bypass data lines and bypass gate lines across multiple layers, the wires can connect to pixels adjacent to the hole while remaining invisible to the human eye, thus maintaining electrical connectivity without degrading image quality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If bypass lines are disposed in the peripheral area to maintain connection, then electrical connectivity is preserved, but the peripheral non-display area expands

Engineering Contradiction:
Improveelectrical connectivityVSAvoiddisplay area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent utilizes vertical stacking in the third dimension to route bypass lines through multiple layers beneath the display surface. This allows the bypass lines to traverse the peripheral area and connect to pixels adjacent to the hole without occupying additional planar space, thereby preserving electrical connectivity while minimizing the expansion of the non-display area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The bypass data lines and bypass gate lines are nested within each other across alternating layers, with bypass data lines positioned between bypass gate lines in a nested alternating arrangement. This nested structure efficiently packs the routing paths into a compact volume beneath the display, minimizing the peripheral area required while maintaining all necessary electrical connections.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Area of stationary object

If bypass data lines and bypass gate lines are alternately disposed in multiple layers, then coupling is reduced and display area is maximized, but device structure becomes more complex

Engineering Contradiction:
Improvedisplay areaVSAvoidline routing structure
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the bypass routing into distinct alternating layers: odd-numbered layers contain bypass data lines while even-numbered layers contain bypass gate lines. This segmentation separates the signal routing functions across different vertical levels, reducing electromagnetic coupling between adjacent lines and enabling tighter packing that maximizes display area while managing structural complexity through systematic layer assignment.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250248252A1Display device and electronic device including the same
Publication Date: 2025.07.31 SAMSUNG DISPLAY CO LTD
  • US20250248252A1 patent drawing
  • US20250248252A1 patent drawing
  • US20250248252A1 patent drawing

AI summary

A display device includes a plurality of data lines disposed in a display area and extending in a first direction, a plurality of gate lines disposed in the display area and extending in a second direction intersecting the first direction, a plurality of bypass data lines electrically connected to the plurality of data lines and disposed in a first peripheral area adjacent to the display area, and a plurality of bypass gate lines electrically connected to the plurality of gate lines, disposed in the first peripheral area, and alternately disposed in at least two layers.