Display Device Vertical Stacking Storage Capacitor Aperture Ratio
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Solution Overview
Problem
Existing organic light-emitting display devices face challenges in increasing the size of driving transistors and improving the aperture ratio of subpixels due to the presence of various lines and circuit elements, which also limits the capacity of storage capacitors.
Innovation Solution
The solution involves a display device structure where the driving transistor and storage capacitor are efficiently disposed on the circuit area of the subpixel, utilizing a multi-layered capacitor configuration that minimizes the number of contact-holes and optimizes the area for the storage capacitor, allowing for increased transistor size and capacitor capacity without adjacent contact-holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the driving transistor is increased to improve driving performance, then the driving performance is improved, but the aperture ratio of the subpixel decreases due to limited area
Solution Approach 1:
The patent utilizes vertical stacking to create multiple capacitor electrodes at different heights (first, second, and third capacitor electrodes on different layers), transforming a two-dimensional area constraint into a three-dimensional spatial solution. This allows the storage capacitor to occupy vertical space rather than horizontal space, enabling the driving transistor to maintain larger area while the capacitor achieves sufficient capacity through multi-layer construction.
Solution Approach 2:
The storage capacitor electrodes are nested within the circuit area by positioning the first capacitor electrode at the bottom, the second capacitor electrode in the middle layer, and the third capacitor electrode at the top layer. This nested arrangement allows multiple capacitor components to occupy overlapping horizontal footprints at different vertical levels, maximizing space utilization and enabling larger transistor area without compromising capacitor capacity.
2Reliability
If the capacity of the storage capacitor is increased to improve driving performance, then the driving performance is improved, but the area occupied by the storage capacitor increases, reducing the aperture ratio
Solution Approach 1:
The patent increases capacitor capacity by adding vertical dimension through multiple electrodes at different heights rather than expanding horizontal area. The first capacitor electrode is disposed at the bottom, the second capacitor electrode is disposed in the middle layer, and the third capacitor electrode is disposed at the top layer, creating a multi-layer capacitor structure that achieves higher capacity within the same horizontal footprint.
Solution Approach 2:
The storage capacitor is constructed as a composite structure with multiple capacitor electrodes (first, second, and third electrodes) and insulating layers between them. This composite multi-layer design allows the capacitor to achieve sufficient capacity by stacking conductive and insulating materials vertically, maximizing space utilization and enabling larger transistor area without compromising capacitor capacity.
3Ease of operation
If various lines and circuit elements are disposed in the subpixel to enable transistor operation, then the transistor can function, but the available area for the driving transistor and storage capacitor is reduced
Solution Approach 1:
The patent resolves area conflicts by transitioning to three-dimensional vertical stacking for the storage capacitor, with electrodes disposed at different heights (bottom, middle, and top layers). This vertical arrangement allows circuit elements to share the same horizontal space at different vertical levels, enabling full transistor functionality while maintaining larger available area for the driving transistor and light-emitting elements.
Data Source
AI summary
Embodiments of the present disclosure are related to a display device, as arranging a storage capacitor and an active pattern disposed on a subpixel by using an active layer that a semiconductor layer and a conductive layer are laminated, an area of the storage capacitor can be increased efficiently and methods can be provided to use an area overlapped with a contact-hole located on the active pattern as an area of the storage capacitor. Furthermore, as a location of the contact-hole is adjusted easily, by making the contact-hole not to be disposed on an area adjacent to a driving transistor, a size of the driving transistor can be increased and an aperture ratio of the subpixel can be improved.