Display Device Clock Data Recovery EMI Reduction
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Solution Overview
Problem
Display devices face challenges in reducing electro-magnetic interference (EMI) generated during clock data recovery (CDR) operations, which are essential for recovering internal reference clocks in data drivers.
Innovation Solution
A display device and control method that embeds a clock signal within image signals, using a CDR unit to extract internal reference clocks during inactive frame periods, with a comparator ensuring frequency alignment and a pulse counter managing operating conditions to minimize EMI by optimizing CDR unit operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CDR unit continuously operates to recover internal reference clock, then clock recovery reliability is improved, but electro-magnetic interference (EMI) increases
Solution Approach 1:
The CDR unit operates periodically rather than continuously. The control method determines specific inactive periods (e.g., vertical blanking intervals) when the CDR unit should operate to recover the reference clock, and other periods when it should remain inactive. This periodic operation maintains necessary clock recovery functionality while significantly reducing EMI generation during non-critical periods.
Solution Approach 2:
The system performs preliminary determination of CDR operating conditions before actual clock recovery operations. The control method evaluates frame control signals and determines in advance whether the CDR unit should be activated in upcoming inactive periods, allowing the system to prepare and execute clock recovery only when necessary, thereby reducing unnecessary EMI.
2Speed
If the CDR unit operates during active frame periods, then clock recovery speed is improved, but image quality deteriorates due to interference
Solution Approach 1:
The invention explicitly schedules CDR operations during inactive periods (vertical blanking intervals) when no image data is being displayed or processed. This timing separation ensures that clock recovery operations do not interfere with active image display, preventing image quality degradation while still achieving timely clock synchronization before the next active frame period begins.
3Measurement precision
If the CDR unit operates frequently, then clock synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The control method implements periodic operation of the CDR unit during inactive periods rather than continuous operation. By limiting CDR activation to specific vertical blanking intervals when clock synchronization is most critical, the system maintains adequate synchronization accuracy while significantly reducing power consumption compared to continuous operation.
Solution Approach 2:
The system performs clock recovery only partially (during selected inactive periods) rather than excessively (continuously). This partial action approach provides sufficient clock synchronization for normal operation while avoiding the excessive power consumption that would result from continuous CDR unit operation.
Data Source
AI summary
A display device includes a display unit including a light emitting device, data and gate driver for respectively applying data and gate voltages to the display unit, and a signal controller for transmitting, to the data driver, image data having a clock embedded therein. The data driver recovers a first internal reference clock during a low period of a first frame control signal, using the image data having the clock embedded therein, compares the frequency of the recovered first internal reference clock with the frequency of a previously stored reference clock, when the frequency of the recovered first internal reference clock is within an error range of the frequency of the previously stored reference clock, outputs the recovered first internal reference clock and receives a second frame control signal, and when the second frame control signal corresponds to a CDR unit operating condition, recovers a second internal reference clock.