Display Device Gray-Scale Voltage Generation Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional active matrix liquid crystal display devices face challenges in reducing chip size due to the increasing number of transistors in decoder circuits required for higher gray scales and resolutions, leading to increased manufacturing costs and power consumption.
Innovation Solution
A display device with a gray-scale voltage generating circuit that generates discontinuous gray-scale voltages, a decoder circuit that selects neighboring voltages based on upper-order bits, and an output amplifying circuit that generates intermediate voltages using lower-order bits, reducing the number of transistors needed in the decoder circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of gray scales is increased to 1024 gray scales, then the display quality and resolution are improved, but the number of transistors in the decoder circuit increases, leading to increased chip size and manufacturing cost
Solution Approach 1:
The patent segments the gray-scale voltage generation process into two stages: a first stage that generates a subset of gray-scale voltages using a reduced decoder circuit, and a second stage that generates additional gray-scale voltages by interpolating between the first-stage voltages. This segmentation allows the system to achieve 1024 gray scales while using a decoder circuit with fewer transistors than would be required for a direct 1024-to-1 decoder.
Solution Approach 2:
The patent applies partial action by generating only a subset of gray-scale voltages (e.g., 512 voltages) in the first stage using the decoder circuit, and then generating the remaining gray-scale voltages through interpolation in the second stage. This partial generation approach reduces the complexity requirement for the decoder circuit while still achieving the full 1024 gray-scale output.
2Device complexity
If the number of transistors in the decoder circuit is reduced to suppress chip size, then manufacturing cost and power consumption are reduced, but the ability to generate all gray-scale voltages directly is compromised
Solution Approach 1:
The patent divides the gray-scale voltage generation into two sequential stages. The first stage uses a simplified decoder circuit with fewer transistors to generate a subset of gray-scale voltages. The second stage uses an interpolation circuit to generate the remaining gray-scale voltages by calculating intermediate values between adjacent first-stage voltages. This segmentation enables chip size reduction while maintaining full gray-scale capability.
Solution Approach 2:
The patent introduces an interpolation circuit as an intermediary between the first-stage decoder and the final gray-scale voltage output. This intermediary circuit generates the additional gray-scale voltages by interpolating between the voltages produced by the reduced decoder circuit, thereby compensating for the reduced transistor count without sacrificing display quality.
3Measurement precision
If a conventional tournament type decoder method is used, then all gray-scale voltages can be generated, but the number of decoder circuits required increases, leading to increased chip size
Solution Approach 1:
The patent segments the decoder function into a first decoder that generates a subset of gray-scale voltages and a second interpolation circuit that generates the remaining voltages. This segmentation reduces the number of transistors required compared to a conventional tournament decoder that would need to directly generate all 1024 gray-scale voltages, thereby reducing chip area.
Solution Approach 2:
The patent uses partial action by having the first decoder generate only a subset of gray-scale voltages (e.g., 512 voltages) rather than all 1024 voltages. The remaining voltages are generated through interpolation in the second stage, which reduces the transistor count and chip area while still achieving complete gray-scale coverage.
Data Source
AI summary
A display device includes a display panel having a plurality of video lines, and a drain driver receiving n-bit display data, and connected to the plurality of video lines. The drain driver includes a gray-scale voltage generating circuit which generates M (M<2n) pieces of gray-scale voltages, a decoder circuit which selects two gray-scale voltages from the M pieces of gray-scale voltages based on upper-order bits of the n-bit display data, an operational amplifier which includes k (k≧3) pieces of non-inverting input terminals and one inverting input terminal connected to an output terminal of the operational amplifier, and a switching circuit which selects the two gray-scale voltages of the decoder circuit, and applies the two gray-scale voltages to the k pieces of non-inverting input terminals of the operational amplifier based on lower-order m (n>m≧2) bits of the n-bit display data.