Display Device Masking via Hole Taper Angles
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Solution Overview
Problem
The manufacturing process of display devices, particularly those using organic light emitting displays, faces inefficiencies due to the need for multiple mask processes, which can lead to increased surface roughness during etching and reduced light efficiency.
Innovation Solution
The use of a hard mask layer or photoresist pattern allows for the reduction of mask processes, preventing surface roughness during dry etching and enabling more efficient deposition of a transparent conductive layer by forming distinct taper angles between via holes and contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to pattern wirings and insulating films, then manufacturing precision is improved, but process complexity and manufacturing time increase
Solution Approach 1:
The patent combines multiple mask processes into a single integrated mask process. The mask layer is used to simultaneously pattern both the via layer (forming via holes) and the insulating film (forming contact holes), eliminating the need for separate mask processes. This merging approach maintains patterning precision while significantly reducing process complexity and manufacturing time.
Solution Approach 2:
The mask layer serves multiple functions: it acts as a pattern template for both via holes and contact holes, provides etching protection for underlying layers, and defines the geometric patterns for different conductive elements. This multi-functionality allows a single mask process to achieve what previously required multiple sequential mask processes.
2Manufacturing precision
If multiple mask processes are performed sequentially, then patterning accuracy is maintained, but manufacturing efficiency decreases
Solution Approach 1:
The patent merges sequential mask processes into a single concurrent patterning operation. By using one mask layer to define both via hole patterns and contact hole patterns simultaneously, the manufacturing process achieves the same patterning accuracy as multiple sequential processes but with significantly improved productivity and reduced cycle time.
3Manufacturing precision
If separate mask processes are used for via holes and contact holes, then manufacturing precision is improved, but light efficiency deteriorates due to increased surface roughness
Solution Approach 1:
The patent combines the patterning of via holes and contact holes into a single mask process, which reduces the number of etching cycles and minimizes cumulative surface roughness. This approach maintains the positioning precision of holes while preserving the smoothness of the via layer surface, thereby improving light efficiency in the display device.
Solution Approach 2:
The patent converts the potential harm of multiple etching processes (which increase surface roughness and reduce light efficiency) into a benefit by using a single integrated etching process. This approach maintains the positioning accuracy advantage while eliminating the surface roughness penalty, effectively turning the constraint into an opportunity for improved optical performance.
4Ease of manufacture
If the same taper angle is used for via holes and contact holes, then manufacturing simplicity is maintained, but short circuits occur due to poor transparent conductive layer deposition
Solution Approach 1:
The patent applies different taper angles to different hole types based on their specific requirements. Via holes are formed with a first taper angle optimized for their depth and diameter, while contact holes are formed with a second taper angle optimized for their geometry and electrical connection requirements. This local differentiation ensures proper transparent conductive layer deposition in each case, preventing short circuits while maintaining manufacturing feasibility.
Solution Approach 2:
The patent changes the etching parameters (specifically the taper angle) based on the type of hole being formed. By adjusting the etching conditions to produce different taper angles for via holes and contact holes, the patent optimizes the deposition characteristics of the transparent conductive layer for each structure type, ensuring reliable electrical connections without compromising process simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves process efficiency and light efficiency by eliminating the need for separate mask processes and reducing surface roughness, thereby preventing short circuits and enhancing the overall performance of the display device.
Implementation Method 1
by using the hard mask layer or the photoresist pattern, it is possible to prevent a surface roughness of the via layer from being increased during a dry etching process
Implementation Method 2
a transparent conductive layer may be more efficiently/effectively deposited in a subsequent process
Data Source
AI summary
A display device and a method of the display device are provided. The display device includes a lower metal layer on a substrate, a buffer layer on the lower metal layer, a first semiconductor layer on the buffer layer, a gate insulating layer on the first semiconductor layer, a first gate electrode on the gate insulating layer, an interlayer insulating layer on the first gate electrode, a via layer on the interlayer insulating layer, a pixel electrode on the via layer and electrically connected to the first semiconductor layer, a light emitting layer on the pixel electrode, a common electrode on the light emitting layer, a first contact hole penetrating the buffer layer and the interlayer insulating layer and a second contact hole penetrating the interlayer insulating layer, and a first via hole and a second via hole each penetrating the via layer.