Display Device Conductive Layer Parasitic Capacitance Reduction
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Solution Overview
Problem
Current display devices face challenges in achieving improved display quality due to parasitic capacitance issues between conductive lines and data lines, which affect the integrity of scan signals and voltage distribution.
Innovation Solution
The display device incorporates a specific configuration of conductive layers, including a second driving voltage line and a second common voltage line on the same layer as pixel electrodes, along with strategically overlapping scan lines to reduce parasitic capacitance and secure sufficient space for storage capacitors, thereby enhancing display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If driving voltage lines and common voltage lines are disposed on separate layers from pixel electrodes, then signal integrity is maintained, but parasitic capacitance between conductive lines and data lines increases
Solution Approach 1:
The patent applies dimensionality change by moving driving voltage lines and common voltage lines from separate layers to the same layer as pixel electrodes (third conductive layer). This spatial reconfiguration reduces the overlap area between conductive lines and data lines in the plan view, thereby reducing parasitic capacitance while maintaining signal integrity through proper electrical connection via branch portions.
Solution Approach 2:
The driving voltage lines and common voltage lines are segmented into multiple portions including main line portions extending in the second direction and branch portions protruding in the first direction. This segmentation allows the lines to be strategically positioned to minimize overlap with data lines while ensuring adequate electrical connection to pixel electrodes, thus reducing parasitic capacitance without compromising signal delivery.
2Object-affected harmful factors
If conductive lines are positioned to minimize overlap with data lines, then parasitic capacitance is reduced, but available space for storage capacitors decreases
Solution Approach 1:
The patent applies local quality by creating different spatial configurations for different portions of the conductive lines. The main line portions extend in the second direction with minimal overlap with data lines to reduce parasitic capacitance, while branch portions protrude in the first direction to provide adequate space and positioning for storage capacitors. This localized differentiation allows simultaneous optimization of both parasitic capacitance reduction and storage capacitor space allocation.
3Object-affected harmful factors
If driving voltage lines and common voltage lines are placed on the same layer as pixel electrodes, then manufacturing complexity increases, but parasitic capacitance is reduced
Solution Approach 1:
The patent merges driving voltage lines, common voltage lines, and pixel electrodes onto the same conductive layer (third conductive layer). This consolidation reduces the total number of conductive layers from four to three, simplifying the overall structure while enabling strategic positioning of line portions to minimize parasitic capacitance. The merged layer allows for integrated optimization of space utilization and electrical performance.
Data Source
AI summary
A display device includes a substrate, a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer and a third conductive layer disposed on the second conductive layer. The first conductive layer includes a data line extending in a first direction. The second conductive layer includes a first scan line extending in a second direction intersecting the first direction, and a second scan line spaced apart from the first scan line and extending in the second direction. The third conductive layer includes a first driving voltage line extending in the second direction, a first common voltage line spaced apart from the first driving voltage line and extending in the second direction, and a pixel electrode disposed between the first driving voltage line and the first common voltage line in a plan view.