Display Device Serial Clock Pixel Circuit Subframe Control

Multiple parallel clock signals for different subframes are merged into a single serial clock signal that sequentially carries timing information for all subframes. This reduces the number of signal lines from multiple parallel connections to a single serial connection, thereby reducing circuit complexity while maintaining the ability to independently control each subframe's light emission through the sequential timing embedded in the serial clock signal.

The patent transforms the control architecture from a spatial dimension (multiple parallel clock signals transmitted simultaneously through separate lines) to a temporal dimension (single serial clock signal transmitted sequentially over time). This dimensional change allows the same control functionality to be achieved with fewer physical signal lines by encoding subframe timing information in the temporal sequence of the serial clock signal.

The serial clock signal operates periodically, sequentially activating control for each subframe in a repeating cycle. This periodic action allows the pixel circuit to maintain precise subframe control capability while remaining in a low-power state during intervals between clock cycles, rather than continuously operating multiple circuits simultaneously. The circuit only performs active processing when triggered by the periodic clock signal edges.

The pixel circuit stores image data and control signals in memory elements before they are needed for actual light emission. This preliminary action allows the circuit to prepare control information in advance during low-power periods, then quickly execute the pre-prepared control actions when clock signal edges occur, achieving precise subframe control without requiring continuous high-power operation of all circuit components.