Display Device Mask Reduction via Three-Tone Lithography
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Solution Overview
Problem
Current display device manufacturing processes require a large number of masks, increasing complexity and costs, particularly in forming the data line and gate wiring, which complicates the fabrication of display devices like LCDs and OLEDs.
Innovation Solution
A method and structure for manufacturing a display device that reduces the number of masks by using a three-tone mask with light transmissive, semi-light transmissive, and light blocking portions to simultaneously form the data line and light blocking pattern, and subsequently forming the gate wiring and pixel electrode in the same process, allowing direct contact between insulating layers over the semiconductor layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional multi-mask processes are used to form data lines and gate wirings separately, then manufacturing precision is maintained, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent combines the formation of data lines and gate wirings into a single mask process. The mask is designed with transparent regions for data lines and gate wirings, and a light blocking pattern that defines both structures simultaneously. This merging of previously separate processes reduces the total number of masks from multiple to just one, simplifying the manufacturing process while maintaining the ability to form both conductive structures with appropriate precision.
2Productivity
If multiple masks are used for forming data line and gate wiring patterns, then pattern precision is achieved, but manufacturing time and costs increase
Solution Approach 1:
The patent merges multiple sequential mask processes into a single simultaneous process. By designing the mask to include both data line patterns and gate wiring patterns with appropriate transparent and blocking regions, the manufacturing cycle is reduced from multiple sequential steps to one integrated step, directly improving productivity and reducing manufacturing time.
Solution Approach 2:
The light blocking pattern is designed in advance to simultaneously define both data line and gate wiring regions. This preliminary design of the mask structure allows both patterns to be formed in a single exposure and development process, eliminating the need for multiple sequential masking operations and reducing overall manufacturing cycle time.
3Manufacturing precision
If separate processes are used for data line and gate wiring formation, then manufacturing precision is maintained, but ease of manufacture decreases
Solution Approach 1:
The patent combines separate data line and gate wiring formation processes into a single integrated mask process. The mask design includes transparent regions that allow light exposure for forming both data lines and gate wirings simultaneously, along with light blocking patterns that define their respective locations. This merging maintains pattern formation accuracy while significantly reducing process complexity.
Solution Approach 2:
The mask is designed with different local properties: transparent regions for conductive material deposition and light blocking patterns for defining structure locations. This local differentiation within the single mask allows precise control over where data lines and gate wirings are formed, maintaining manufacturing precision while simplifying the overall process by eliminating the need for multiple specialized masks.
Data Source
AI summary
A display device includes: a substrate including first and second light-blocking areas, and a pixel area; a light-blocking pattern at least partially at the first light-blocking area; a data line at the second light-blocking area; a first insulating layer on the light-blocking pattern and the data line; a semiconductor layer on the first insulating layer and overlapping the light-blocking pattern on a plane; a second insulating layer on the semiconductor layer; a color filter on the second insulating layer at least partially at the pixel area; a third insulating layer on the second insulating layer and the color filter; a gate line on the third insulating layer at the first light-blocking area; a pixel electrode at least partially at the pixel area; and a bridge electrode at least partially at the first light-blocking area. The second and third insulating layers directly contact one another over the semiconductor layer.