Display Discharge Circuit With Delayed VCOM Release
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Solution Overview
Problem
Display devices using GOA technology face issues with slow discharge from the VCOM terminal during shutdown, leading to residual charges and voltage differences across liquid crystals, causing picture flicker or image sticking upon startup due to inadequate discharge speed.
Innovation Solution
A discharging circuit comprising a control circuit, a time delay circuit, a first discharging circuit, and a second discharging circuit, where the control circuit controls the potential of the first node to switch on the first discharging circuit, and the time delay circuit delays the switch-on of the second discharging circuit to release residual charges through the common voltage terminal and data signal terminal, ensuring synchronized discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If GOA technology is used to reduce connection points between VCOM and display panel, then device complexity and manufacturing cost are reduced, but discharge speed from VCOM becomes too slow causing residual charges
Solution Approach 1:
The discharge function is segmented into two independent discharge circuits: a first discharge circuit for discharging data signal terminal and a second discharge circuit for discharging common voltage terminal. This segmentation allows each circuit to be optimized for its specific discharge task, enabling fast discharge without requiring multiple VCOM connection points.
Solution Approach 2:
The control circuit performs preliminary action by controlling the first discharge circuit to discharge the data signal terminal before the second discharge circuit discharges the common voltage terminal. This preliminary discharge action ensures that residual charges are removed in a controlled sequence, solving the slow discharge problem without adding connection points.
2Reliability
If discharge time is extended to ensure complete discharge, then residual charges are eliminated, but productivity and response time are reduced
Solution Approach 1:
The control circuit implements preliminary discharge action by activating the first discharge circuit before the second discharge circuit. This ensures that the data signal terminal is discharged first, and only then the common voltage terminal is discharged, achieving complete discharge without excessive delay.
Solution Approach 2:
The time delay circuit dynamically controls the switching timing of the second discharge circuit, creating an optimized discharge sequence. This dynamic timing control ensures complete discharge while minimizing the total discharge time, balancing reliability and productivity.
3Device complexity
If voltage difference across liquid crystals is not eliminated, then circuit simplicity is maintained, but display quality deteriorates with flicker and image sticking
Solution Approach 1:
The discharge function is segmented into two independent discharge circuits: a first discharge circuit for discharging data signal terminal and a second discharge circuit for discharging common voltage terminal. This segmentation allows each circuit to be optimized for its specific discharge task, ensuring complete voltage equalization without compromising display quality.
Solution Approach 2:
The control circuit uses feedback from the shutdown signal to activate the discharge circuits in a controlled sequence. This feedback mechanism ensures that discharge operations are triggered at the appropriate moment, completely eliminating voltage differences and preventing display artifacts while maintaining circuit simplicity.
Data Source
AI summary
The present disclosure relates to a discharging circuit and a driving method thereof, and a display device. The discharging circuit of the present disclosure includes a control circuit, a time delay circuit, a first discharging circuit and a second discharging circuit. The control circuit is configured to control potential of a control signal output terminal of the control circuit. The time delay circuit is configured to delay a switched-on time of the second discharging circuit. The first discharging circuit is configured to pull down a potential of a data signal terminal to a potential of a common voltage terminal, under control of a control signal output from the control circuit. The second discharging circuit is configured to release the potential of the common voltage terminal and the potential of the data signal terminal under the control of the time delay circuit.