Display Drive Circuit Signal Delay Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional display apparatuses face signal delay and prolonged fall time due to resistant components and stray capacitance in the wiring of gate bus lines, especially in large-sized panels, where longer wiring lengths exacerbate these issues.
Innovation Solution
A drive circuit with multiple shift registers connected to each other, incorporating switching elements and a control unit that applies a predetermined electric potential to control the output node, allowing the drive signal to fall to a lower potential than the clock signal's low level, thereby reducing signal delay and fall time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If gate bus lines are arranged through almost the entire display panel to connect the gate driver on one edge to all pixel rows, then the display panel can be driven sequentially row by row, but the resistant component and stray capacitance of the long wiring cause delay and prolonged fall time of the drive signal
Solution Approach 1:
The gate driver is divided into multiple independent gate drivers distributed at different edges of the display panel. Each gate driver independently drives a portion of the gate bus lines, segmenting the single long wiring path into multiple shorter segments. This reduces the total wiring length from one edge to all pixel rows, thereby reducing resistant component and stray capacitance, which suppresses signal delay and shortens fall time while maintaining sequential row-by-row driving capability
Solution Approach 2:
Instead of placing all gate drivers at one edge (one-dimensional arrangement), the invention distributes gate drivers to multiple edges of the display panel (two-dimensional arrangement). This spatial redistribution reduces the average wiring length from gate drivers to pixel rows by utilizing the panel's perimeter in multiple directions, effectively reducing RC time constants and improving signal timing characteristics
2Area of stationary object
If the wiring length is increased to cover large size display panels, then the display area is expanded, but the resistant component and stray capacitance increase, resulting in more significant delay of drive signal
Solution Approach 1:
For large size display panels, the gate driver functionality is segmented into multiple independent gate drivers positioned at different edges. Each gate driver handles a subset of gate bus lines, converting one long wiring path into multiple shorter paths. This segmentation reduces the maximum wiring length and total RC accumulation, suppressing signal delay even as display panel area increases
Solution Approach 2:
The invention applies different wiring arrangements to different regions of the display panel by distributing gate drivers to multiple edges. Each local region has optimized wiring length from its nearest gate driver, creating locally optimal signal paths. This allows large panel areas to be driven without uniform long wiring delays across the entire panel
Data Source
AI summary
Provided are a drive circuit and a display apparatus capable of suppressing the delay of a drive signal. Each of multiple shift registers comprises: an output switching element to which a predetermined clock signal to be input, the output switching element comprising a second controlled terminal is connected to an output node from which a drive signal is output; a first input switching element comprising a first controlled terminal to which a set signal to be input and a second controlled terminal connected to the output switching element; and a control unit for applying a predetermined electric potential to the second controlled terminal of the output switching element, wherein a low-level electric potential of the predetermined clock signal is lower than a low-level electric potential of the drive signal, and the predetermined electric potential is applied to the output switching element when the predetermined clock signal falls.