Display Driver Buffer Amplifier Offset Reduction
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Solution Overview
Problem
Display devices, particularly those with OLED panels, face challenges in achieving high precision in source voltages due to manufacturing variations in buffer amplifiers, leading to color unevenness in single-color image regions, as low precision results in different output voltages for the same image data.
Innovation Solution
A display driver configuration that includes a differential input circuit with MISFETs and an active load circuit, along with connection switches and a controller to control these switches based on image data, effectively reduces offset voltage differences between adjacent buffer amplifiers by electrically connecting them when driving pixels with the same grayscale levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If element sizes are increased to reduce mismatching among circuit elements in the differential input circuit and active load circuit, then manufacturing precision of source voltages is improved, but device complexity and cost increase due to increased parasitic capacitance and reduced operation speed
Solution Approach 1:
The patent merges adjacent buffer amplifiers into a shared structure where the differential input circuit and active load circuit are common to multiple buffer amplifiers. This sharing of circuit elements reduces the total number of components and parasitic capacitance while maintaining manufacturing precision through the common-mode rejection capability of the differential configuration.
Solution Approach 2:
The shared differential input circuit and active load circuit serve multiple buffer amplifiers simultaneously, making these components multi-functional. This universal structure reduces overall device complexity and parasitic capacitance while the differential configuration ensures precise voltage matching across all connected buffer amplifiers.
2Manufacturing precision
If element sizes are increased to reduce mismatching among circuit elements, then manufacturing precision of source voltages is improved, but operation speed decreases
Solution Approach 1:
By merging adjacent buffer amplifiers to share the differential input circuit and active load circuit, the patent reduces the total capacitance load on each circuit element. This shared architecture maintains manufacturing precision through common-mode rejection while improving operation speed by reducing the RC time constants associated with larger individual elements.
3Ease of operation
If buffer amplifiers are designed with low output impedance to drive source lines with large load capacitance, then ease of operation is improved, but manufacturing precision deteriorates due to random offset voltages from mismatching semiconductor elements
Solution Approach 1:
The patent employs a differential input circuit configuration where mismatching of semiconductor elements creates offset voltages that are rejected through the differential mode operation. The asymmetric mismatching effects in individual transistors are compensated by the symmetric differential structure, allowing low output impedance for driving capability while maintaining manufacturing precision.
Solution Approach 2:
The patent converts the harmful effect of random offset voltages from mismatching semiconductor elements into a beneficial common-mode signal that is rejected by the differential configuration. The mismatching that would normally degrade precision instead creates signals that are naturally suppressed by the differential structure, allowing low output impedance design without sacrificing manufacturing precision.
4Productivity
If the same image data are supplied for pixels in a single-color region, then productivity is improved, but manufacturing precision deteriorates due to low precision source voltages resulting in different output voltages
Solution Approach 1:
The patent merges adjacent buffer amplifiers to share the differential input circuit and active load circuit, ensuring that even when the same image data is supplied to multiple pixels for productivity, the shared precision reference circuitry maintains consistent output voltages. This prevents color unevenness in single-color regions while maintaining the efficiency of processing identical data.
Data Source
AI summary
a display driver is provided which drives a display panel. The display driver includes first and second buffer amplifiers associated with first and second pixels positioned adjacent in a horizontal direction; first and second connection switches; and a controller. Each of the first and second buffer amplifiers includes: a differential input circuit including a MOS transistor pair, first and second drain interconnections; an active load circuit connected to the first and second drain interconnections; and an output stage. The first connection switch is connected between the output nodes of the first and second buffer amplifiers. The second connection switch is connected between the first drain interconnections of the first and second buffer amplifiers. The controller controls the first and second switches in response to image data associated with the first and second pixels.