Display Driver Clock Control for Power Reduction
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Solution Overview
Problem
The MIPI-DSI interface's high-speed mode increases power consumption in display drivers, which is undesirable, especially in portable devices where multifunctionality demands reduced power usage.
Innovation Solution
A display driver system that includes an interface circuit for clock recovery and a control circuit to generate an internal clock signal, allowing the driver to synchronize data transmission with either a recovered clock or an external clock, optimizing power usage by controlling clock signal output based on packet types and sync periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the MIPI-DSI interface operates in high-speed mode to transmit image data, then data transmission speed is improved, but power consumption of the display driver increases
Solution Approach 1:
The patent implements periodic action by selectively stopping the internal clock signal during non-essential periods (such as horizontal sync periods without image data transmission) while maintaining clock operation during essential periods (image data transmission). This periodic on-off operation reduces overall power consumption while preserving high-speed transmission capability when needed, directly resolving the contradiction between transmission speed and power consumption.
2Reliability
If the internal clock signal is continuously output to support high-speed data transmission, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the internal clock signal output dynamic rather than static. The clock signal is selectively generated or stopped based on the type of reception packet and synchronization period conditions. This dynamic adjustment ensures the clock is active only when necessary for reliable data transmission, reducing power consumption while maintaining transmission reliability during critical periods.
3Adaptability or versatility
If the display driver supports multifunctionality with advanced features, then device functionality is improved, but power consumption increases
Solution Approach 1:
The patent implements partial action by applying clock signal suppression selectively to specific periods (horizontal sync periods without image data) while maintaining full clock operation during image data transmission periods. This partial application of clock stopping achieves power savings without compromising the multifunctionality and advanced features of the display driver, as the clock remains available when needed for various functions.
Data Source
AI summary
A display device includes a display panel and a display driver driving the display panel. The display driver is connected to a host with a clock lane and at least one a data lane. The display driver includes: an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal; a control circuit configured to output an internal clock signal synchronous with the external clock signal; and a drive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal fed from the control circuit. The control circuit is configured to feed the internal clock signal in response to a type of a reception packet included in the reception data.