Display Driver Clock Recovery via Embedded Sync Signals
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Solution Overview
Problem
Conventional display driver systems face issues with phase drifts between clock and image data signals, leading to improper data retrieval, increased power consumption, and complex circuitry noise interference, especially in high-frequency applications.
Innovation Solution
A method where synchronization information is embedded between image data packets, allowing the data driver to extract a synchronizing signal and generate an internal clock signal for precise image data retrieval, using a timing signal with phase-delayed pulses to overlap with synchronization and image data portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the clock signal is incorporated in the transmitted stream of image data, then no separate clock signal line is required, but power consumption increases and circuitry becomes more complex and susceptible to noise interference
Solution Approach 1:
The patent extracts the clock signal from the image data stream by detecting transitions in the image data itself. Instead of embedding the clock signal within the data stream, the system uses the inherent edges or transitions in the image data to generate the clock signal at the receiver端, thereby separating the clock recovery function from the data transmission path and avoiding the need for complex embedded clocking circuits.
Solution Approach 2:
The image data stream serves its own clocking function by providing transitions that can be detected to generate the clock signal. The data stream itself contains the necessary information (transitions/edges) to regenerate the clock signal, eliminating the need for a separate embedded clock signal and reducing overall system complexity and power consumption.
2Device complexity
If the clock signal is incorporated in the transmitted stream of image data, then no separate clock signal is required, but the driving system has larger layout area and more complex circuitry affected by noise interference
Solution Approach 1:
The patent extracts the clock signal generation function from the data transmission path by using transition detection circuits that operate independently. The clock signal is regenerated at the receiver端 based on detected transitions in the incoming data stream, separating clock recovery from the main data processing path and reducing susceptibility to noise.
Solution Approach 2:
The patent introduces transition detection circuits as intermediary elements that convert the incoming image data stream into a regenerated clock signal. These intermediary circuits act as a buffer between the noisy transmission channel and the sensitive clocking logic, isolating the system from noise interference while maintaining accurate timing.
3Reliability
If separate signal lines are used for clock and image data, then phase drifts occur at high frequencies, but the clock signal can be transmitted reliably
Solution Approach 1:
The patent implements a dynamic clock recovery mechanism where the clock signal is continuously regenerated based on real-time detection of transitions in the incoming data stream. This dynamic approach allows the system to automatically adjust to frequency variations and maintain phase alignment without requiring ultra-precise fixed-frequency transmission, solving the phase drift problem at high frequencies.
Solution Approach 2:
The system changes the parameter of clock signal generation from fixed-frequency transmission to dynamic regeneration based on detected transitions. By adjusting the clock signal parameters locally at the receiver端 based on actual received data characteristics, the system maintains reliable transmission while preventing phase drift accumulation.
Data Source
AI summary
In a display driver, image data are assembled with synchronization information to form a stream of digital data. The stream of digital data is transmitted from a timing controller to a data driver along with a timing signal having phase-delayed pulses obtained from an external clock received by the timing controller. In response to the timing signal, the data driver can extract a synchronizing signal from the synchronization information embedded in the stream of digital data, and use the synchronizing signal for generating an internal clock signal. Encoded image data in the stream of digital data then can be retrieved according to the internal clock signal.