Display Driver IC Clock Synchronization for Low-Power Flicker Control
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Solution Overview
Problem
The synchronization of operating clocks between application processors and display driver integrated circuits in low frame rate scenarios can lead to flicker on display panels due to differing frequencies, especially in low-temperature polycrystalline oxide panels that switch to a video mode for data retention, increasing power consumption and manufacturing costs.
Innovation Solution
A display driver integrated circuit and system-on-chip design that includes a clock generator and control circuit to synchronize internal operating clocks through sync request signals, allowing for frequency adjustments during low power mode periods to maintain consistent clock frequencies between the application processor and display panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If video mode interfacing is applied to leverage LTPO panel's data retention capability, then screen update frequency is reduced and manufacturing cost is lowered, but power consumption increases due to different clock frequencies between AP and DDIC
Solution Approach 1:
The patent implements dynamic clock frequency adjustment where the DDIC can operate at different clock frequencies (e.g., 24Hz during LPM, 60Hz during active periods) based on system needs. The control circuit adjusts the clock frequency dynamically to match the AP's refresh rate, enabling video mode operation while maintaining synchronized timing and reducing power consumption.
2Use of energy by moving object
If system operates at low frame rate to reduce power consumption, then power usage is reduced, but flicker occurs due to desynchronized clock frequencies between AP and DDIC
Solution Approach 1:
The patent employs feedback mechanisms where the DDIC monitors its own clock frequency and the AP's clock frequency, and the control circuit adjusts the DDIC's clock frequency based on the detected frequency difference. This feedback loop ensures that even at low frame rates, the clock frequencies remain synchronized, preventing flicker while maintaining low power consumption.
Solution Approach 2:
The patent changes the clock frequency parameter dynamically based on operating conditions. During low power mode, the DDIC operates at a lower frequency (24Hz) matching the AP's low frame rate output, while during active periods it switches to a higher frequency (60Hz). This parameter adjustment maintains synchronization and eliminates flicker across different operating states.
3Device complexity
If clock frequencies between AP and DDIC are allowed to differ to reduce synchronization complexity, then system complexity is reduced, but image quality deteriorates due to flicker
Solution Approach 1:
The DDIC performs self-adjustment of its clock frequency based on feedback from the AP's clock signals. The control circuit automatically detects frequency differences and adjusts the DDIC's internal clock without requiring complex external synchronization mechanisms from the AP side. This self-service approach maintains image quality while reducing overall system complexity.
Data Source
AI summary
A display driver integrated circuit, System-On-Chip, and display system including the System-On-Chip are provided. A display driver integrated circuit (IC) includes: a clock generator configured to generate an internal operating clock; and a control circuit configured to provide a data signal to a pixel array based on the internal operating clock, wherein the data signal corresponds to frame data, wherein the control circuit is further configured to, in a frame data update period: receive first frame data, perform a first synchronization operation on the internal operating clock based on the first frame data, and provide a first data signal to the pixel array, and wherein the control circuit is further configured to, in a low power mode (LPM) period when an update of the frame data is not performed: transmit a sync request signal based on a result of monitoring a state of a display panel, receive a frequency signal from a System-on-Chip (SoC) in response to the sync request signal, and perform a second synchronization operation on the internal operating clock based on the frequency signal.