Unified Clock Distribution for Display Driver Synchronization
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Solution Overview
Problem
In multi-display driver circuit systems, frequency errors between internal clock frequencies of different display driver circuits lead to suboptimal display performance due to unsynchronized clock signals for GOA, vertical synchronization, horizontal synchronization, and emission control, affecting frame and row synchronization.
Innovation Solution
Each display driver circuit receives a unified clock signal from a main controller to generate synchronized GOA, vertical synchronization, horizontal synchronization, and emission control signals, ensuring all signals are based on a common frequency, reducing errors and improving display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple display driver circuits use internal clock signals independently, then each circuit can operate autonomously, but frequency errors occur between different circuits leading to poor display performance
Solution Approach 1:
The patent merges the clock signal sources of multiple display driver circuits by introducing a unified clock signal from a main controller that is distributed to all auxiliary display driver circuits. This combining approach eliminates frequency errors between circuits while maintaining autonomous operation capabilities through synchronized clock timing.
Solution Approach 2:
The main controller acts as an intermediary that generates and distributes the unified clock signal to multiple display driver circuits. This mediator ensures all circuits operate on the same frequency standard, resolving the frequency error issue while allowing each circuit to maintain its independent functionality.
2Reliability
If a main display driver circuit sends clock signals to auxiliary circuits for synchronization, then vertical and horizontal synchronization is achieved, but GOA clock signals remain unsynchronized affecting display quality
Solution Approach 1:
The patent segments the clock signal distribution into two distinct paths: one for generating synchronized vertical and horizontal signals, and another for generating GOA clock signals. By separately managing these clock distributions from the main controller, both synchronization requirements are met simultaneously, improving overall display quality.
3Ease of manufacture
If internal clock frequencies differ between display driver circuits, then each circuit can be designed independently, but timing errors occur in GOA, vertical synchronization, horizontal synchronization, and emission control signals
Solution Approach 1:
The main controller is designed as a universal clock source that serves multiple functions: generating the unified clock signal, distributing it to all auxiliary circuits, and ensuring synchronized operation of GOA, vertical synchronization, horizontal synchronization, and emission control signals. This multi-functional approach maintains independent circuit design while achieving precise timing synchronization.
Data Source
AI summary
An electronic device includes a display including a first display area and a second display area. The electronic device further includes a main controller configured to send a first clock signal separately to a first display driver circuit and a second display driver circuit. The first display driver circuit is configured to receive the first clock signal and to output a first GOA clock signal to the display. The first GOA clock signal is generated based on the first clock signal. The second display driver circuit is configured to receive the first clock signal, and is further configured to output a second GOA clock signal to the display. The second GOA clock signal is generated based on the first clock signal.