Display Driver Circuit With Control Capacitor for Noise-Stable Setting Signals

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Solution Overview

Problem

Existing driver circuits for display devices suffer from inaccuracies in setting signals due to noise interference from high-frequency signals, affecting the accuracy of signal control.

Innovation Solution

The driver circuit incorporates a control node connected to a control capacitor and a control transistor, with a setting transistor and a control capacitor to stabilize the setting signal, enhancing its accuracy by reducing noise interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional driver circuit structure is used, then the circuit is simple, but the setting signal accuracy deteriorates due to noise interference from high-frequency signals

Engineering Contradiction:
Improvesetting signal accuracyVSAvoidnoise interference
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a control node as an intermediary between the clock signal source and the setting signal output. This control node acts as a mediator that isolates the setting signal path from high-frequency noise in the clock signal path, thereby improving setting signal accuracy without requiring complete circuit restructuring

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the control node and control capacitor from the conventional driver circuit structure to create a separate control path. By taking out these elements, the setting signal generation is separated from the clock signal path, eliminating noise interference while maintaining circuit simplicity

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If noise interference is reduced through additional filtering components, then setting signal accuracy improves, but device complexity increases

Engineering Contradiction:
Improvesetting signal accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The control node serves as a minimal intermediary structure that provides noise isolation without requiring complex filtering components. This approach improves setting signal accuracy while adding only one node and one capacitor, thereby avoiding significant increases in device complexity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the electrical parameters at the control node (voltage levels, timing characteristics) to optimize noise rejection. By adjusting these parameters rather than adding complex filtering structures, the patent achieves improved signal accuracy with minimal circuit complexity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution stabilizes the setting signal, ensuring accurate output of driving signals and reducing power consumption by allowing variable refresh rates on an area-by-area basis in display devices.

Implementation Method 1

a control node, a control capacitor, and a control transistor whose gate terminal is connected to the control node. The control node is connected to a first conducting terminal of the control transistor via the control capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20260018103A1Driver circuit and display device
Publication Date: 2026.01.15 SHARP DISPLAY TECHNOLOGY CORP
  • US20260018103A1 patent drawing
  • US20260018103A1 patent drawing
  • US20260018103A1 patent drawing

AI summary

A driver circuit for driving a plurality of signal lines, the driver circuit includes a plurality of unit circuits including an nth unit circuit, wherein the nth unit circuit includes a clock terminal through which a clock signal is inputted, a setting terminal through which a setting signal is outputted to another unit circuit, a setting transistor connected to the clock terminal and the setting terminal, a control node, a control capacitor, and a control transistor whose gate terminal is connected to the control node, the control node is connected to a first conducting terminal of the control transistor via the control capacitor, and a second conducting terminal of the control transistor is connected to the clock terminal.