Display Driver DAC Decoder Layout for Wide Voltage Selection
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Solution Overview
Problem
Existing digital-to-analog converter circuits for liquid crystal display (LCD) and organic light-emitting diode (OLED) drivers face challenges in achieving a broad output voltage range while maintaining low power consumption and high operational speed, leading to increased decoder area and wiring complexity due to the need for CMOS switch configurations and larger transistor sizes.
Innovation Solution
A digital-to-analog converter circuit with a decoder that selects multiple voltages from a reference voltage ensemble using a combination of sub-decoders of different conductivity types, reducing the number of transistor switches in CMOS configuration and suppressing the increase in gate widths of non-CMOS transistor switches to minimize decoder area and wiring complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a broad output voltage range is achieved using conventional digital-to-analog converter circuits, then the voltage selection capability is improved, but the decoder area and wiring complexity increase due to CMOS switch configurations and larger transistor sizes
Solution Approach 1:
The reference voltage ensemble is divided into multiple subsets, with each subset handled by a dedicated sub-decoder. This segmentation allows the overall decoder to achieve broad voltage coverage without requiring a single large complex decoder, thereby reducing total decoder area and wiring complexity while maintaining extensive voltage selection capability.
Solution Approach 2:
The patent transitions from a single-plane decoder architecture to a multi-level hierarchical structure where sub-decoders operate in parallel and their outputs are combined. This dimensional change in architecture allows voltage selection across a broad range without proportionally increasing decoder area, as the complexity is distributed across multiple smaller units rather than concentrated in one large decoder.
2Speed
If operational speed is maintained at high levels, then the converter performance is improved, but power consumption increases
Solution Approach 1:
The decoder is segmented into multiple sub-decoders that operate in parallel, allowing the conversion operation to be completed faster (improving speed) while each sub-decoder consumes less power individually. The total power consumption is distributed across multiple low-power units rather than concentrated in one high-speed unit, achieving a better speed-power tradeoff.
3Device complexity
If the number of transistor switches in CMOS configuration is reduced, then the decoder area is minimized, but the voltage selection capability may be compromised
Solution Approach 1:
The reference voltage ensemble is segmented into multiple subsets, each subset being selectable by a sub-decoder using fewer transistor switches. While each individual sub-decoder has reduced switch count, the collective capability of all sub-decoders maintains comprehensive voltage selection coverage, thus preserving adaptability while reducing total transistor count and decoder area.
Solution Approach 2:
Multiple sub-decoders are designed with similar circuit structures that can be replicated, creating a universal building block approach. This allows the system to achieve broad voltage selection capability through repetition of efficient, area-minimized sub-decoder units rather than requiring a single large complex decoder with many more transistors.
Data Source
AI summary
Provided first and second reference voltage set wherein the first reference voltage set includes a part or all of reference voltages of the second reference voltage set, and a decoder including first and second sub-decoder sections that select Q reference voltages from first and second reference voltage sets according to upper bits of the input digital signal and transfer the so selected reference voltages to the first to Qth nodes, and third and fourth sub-decoder sections that select first and second voltages from the Q reference voltages transferred to the first to Qth nodes according to lower bits of the input digital signal and transfer the so selected voltages to the first to Pth nodes. The first and third sub-decoder sections are made up of first conductivity type transistors, while the second and fourth sub-decoder sections are made up of second conductivity type transistors. Also provided an amplifier circuit takes a weighted average of voltages at the first to Pth nodes at a preset weighting factors and outputs the weighted average voltage at an output terminal as an analog signal corresponding to the input digital signal.