Display Driver Delay Control for Synchronized Pixel Timing
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Solution Overview
Problem
Existing display drivers face challenges in accurately matching the timing of pixel drive signals across large and high-definition display panels, leading to noise generation and display unevenness due to increased current and gate signal blunting, especially at the central portion of the screen, which is exacerbated by the division of source drivers into multiple IC chips.
Innovation Solution
A display driver system with a delay control circuit that generates and selects delay timing signals to output pixel drive signals at timings that follow a quadratic curve, reducing the increase rate of delay time from the ends to the central portion of the screen, ensuring synchronized timing across multiple drivers without causing display unevenness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the source driver is divided into multiple IC chips, then the device complexity is reduced and ease of manufacture is improved, but the output timing matching between adjacent drivers becomes difficult and display unevenness is caused
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal delay times for each output channel in a lookup table before operation. The delay control circuit retrieves these predetermined delay times based on the output channel number, ensuring accurate timing synchronization between multiple drivers without requiring complex real-time calculations or adjustments at boundaries.
2Area of stationary object
If the gate line length is increased to accommodate large-size display panels, then the display size is improved, but the gate signal waveform becomes blunted due to wiring resistance and timing deviation increases
Solution Approach 1:
The patent applies local quality by implementing position-dependent delay compensation. The delay control circuit determines the output channel number corresponding to each data line and applies specific delay times tailored to the spatial position of the display cell. This ensures that cells at different positions (ends versus central portion) receive gate signals with appropriately compensated timing, correcting waveform blunting effects caused by varying line lengths.
3Measurement precision
If the number of source lines is increased for high-definition display panels, then the definition is improved, but the current amount and noise increase due to simultaneous current flow
Solution Approach 1:
The patent applies periodic action by implementing sequential scanning of gate lines. Instead of simultaneously activating all source lines, the gate driver sequentially selects and activates individual gate lines in a periodic manner. This time-division multiplexing approach limits the number of source lines receiving drive voltage at any given moment, thereby reducing peak current demand and associated noise while maintaining high-definition capability.
Data Source
AI summary
A delay control circuit generates output timing signals that cause pixel drive signals to be output at timings after elapse of different delay times. The delay control circuit includes: first to sth delay timing signal generation circuits, generating first to kth delay timing signals that bring about output timings increasing in delay time; a control signal generation circuit, supplying a start pulse signal that initiates generation of the first to kth delay timing signals to the first to sth delay timing signal generation circuits; and a delay signal selection circuit, for each output channel with respect to first to sth delay timing signal groups each including the first to kth delay timing signals, selecting from among s delay timing signals the delay timing signal that brings about an earliest output timing, and setting the delay timing signals as the first to kth output timing signals.