Display Driver Chip Layout With Dual-Depth Trenches for Isolation
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Solution Overview
Problem
The integration of source and gate drivers into a single chip for bezel-less displays requires distinct manufacturing processes for semiconductor elements with different operating voltages, complicating the element isolation layer design and manufacturing.
Innovation Solution
A semiconductor device is designed with dual depth trenches and varying trench depths for different semiconductor elements, allowing for the integration of high voltage semiconductor elements for both source and gate drivers into a single chip, with a dual depth trench structure in contact regions for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate manufacturing processes are used for source and gate semiconductor elements with different operating voltages, then electrical isolation is achieved, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent divides the isolation structure into multiple depth levels - shallow trenches for low voltage regions and deep trenches for high voltage regions. This segmentation allows each region to have appropriately sized isolation structures, achieving effective electrical isolation while using a unified manufacturing process that forms trenches at different depths for different semiconductor elements
Solution Approach 2:
The patent applies different trench depths to different spatial locations based on voltage requirements. Low voltage semiconductor elements use shallow trenches while high voltage elements use deep trenches. This local differentiation enables optimized isolation for each region's specific electrical characteristics while maintaining process integration
2Reliability
If separate manufacturing processes are used for source and gate semiconductor elements, then electrical isolation is ensured, but manufacturing costs and time increase
Solution Approach 1:
The patent merges the isolation processes for high voltage and low voltage semiconductor elements into a single unified manufacturing process. The process sequentially forms shallow trenches and deep trenches in one integrated flow, eliminating the need for separate manufacturing processes and thereby improving productivity and reducing manufacturing time
Solution Approach 2:
The patent performs preliminary trench formation actions in a predetermined sequence - first forming shallow trenches, then forming deep trenches. This preliminary structuring allows subsequent processing steps to proceed efficiently without requiring rework or additional isolation measures, thereby enhancing manufacturing productivity
Data Source
AI summary
A first high voltage semiconductor element, disposed in a substrate, includes first trenches; a first source region and a first drain region; first drift regions having respective ones partially surround the first source region and the first drain region; a first gate insulating layer and a first gate electrode disposed between the first drift regions; and a first high voltage well surrounding the first drift regions. A second high voltage semiconductor element, disposed in the substrate, includes second trenches; a second source region and a second drain region; second drift regions having respective ones partially surround the second source region and the second drain region; a second gate insulating layer and a second gate electrode disposed between the second drift regions; and a second high voltage well surrounding the second drift regions. Depths of the second trenches are disposed to be greater than depths of the first trenches.