Display Driver Signaling With Embedded Clock to Reduce EMI
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Solution Overview
Problem
Conventional display driving systems face issues with impedance mismatch, electromagnetic interference (EMI), and increased complexity and cost due to the high number of signal lines required for high-speed data transmission, particularly in large screen and high-resolution displays, where multi-drop schemes cause signal distortion and overloading, and PPDS schemes suffer from clock delay and increased line complexity.
Innovation Solution
A display driving system using single level signaling with embedded clock signals, where a clock signal of the same level is embedded between data signals and transmitted through a single line, allowing the panel driving section to recover the clock signal and sample data, thereby minimizing signal lines, EMI, and preventing skew and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-drop scheme is used to share data and clock signal lines among column driving sections, then the timing controller can be used irrespective of the number of outputs, but signal distortion by reflection waves is caused and electromagnetic interference (EMI) increases due to impedance mismatch
Solution Approach 1:
The patent divides the transmission path into point-to-point connections between the timing controller and each column driving section. Each connection has its own dedicated data and clock signal lines, eliminating the multi-drop configuration. This segmentation resolves impedance mismatch issues and reduces EMI by ensuring proper signal matching at each receiver without reflection waves from multiple connection points.
2Object-affected harmful factors
If independent data lines are formed between timing controller and each column driving section in PPDS, then impedance mismatch and EMI are overcome, but the number of signal lines increases and connection complexity increases
Solution Approach 1:
The patent merges the data signal transmission and clock signal transmission into a single integrated signal line. The clock signal is embedded within the data signal transmission path, allowing both signals to share the same physical conductor. This merging reduces the total number of signal lines while maintaining the point-to-point connection benefits that eliminate impedance mismatch and EMI issues.
3Productivity
If data is transmitted at high speed from timing controller to column driving sections, then data transmission speed is improved, but electromagnetic interference (EMI) is caused and signal level must be decreased
Solution Approach 1:
The patent uses an embedded clock signal as an intermediary reference within the data transmission path. By embedding the clock signal within the data signal line and using it as a timing reference for sampling, the system achieves high-speed data transmission with reduced EMI. The embedded clock provides synchronization without requiring a separate high-speed clock line that would generate additional electromagnetic interference.
Data Source
AI summary
A display driving system includes a timing control section having an LVDS receiving unit for receiving data signals, a data processing unit for temporarily storing the data signals, processing the data signals and outputting processed data signals, a timing generation unit for generating clock signals and timing control signals, and a transmission unit for transmitting the data signals; and a panel driving section having row driving units for sequentially emitting gate signals toward a display panel and column driving units for receiving the signals transmitted through signal lines from the transmission unit and supplying the received signals to the display panel. In the timing control section, the transmission unit has driving parts which embed the clock signals between the data signals at the same level and generate and output single level transmission data.