Display Driver Module With Dual-Terminal Gate-Line Control
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Solution Overview
Problem
Single-sided Gate On Array (GOA) drive in display technologies leads to large signal delay at the far terminal of a gate line, causing poor display due to far-terminal signal overcharging and pixel voltage differences between far and near terminals.
Innovation Solution
A driver module with a first and second control unit, each containing control circuits and driver circuits, is designed to control the terminals of gate lines to receive ineffective voltage signals when the drive signal changes, reducing signal delay by simultaneously pulling down both far and near terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single-sided GOA drive is adopted, then device complexity is reduced and ease of manufacture is improved, but signal delay at far terminal increases causing poor display quality
Solution Approach 1:
The gate line is divided into two terminals (first terminal and second terminal) with separate control mechanisms. The first control circuit controls the first terminal while the second control circuit controls the second terminal, allowing independent optimization of each segment to reduce signal delay and improve display quality while maintaining manufacturing simplicity.
Solution Approach 2:
The patent applies different voltage parameters to different terminals of the gate line. The first control circuit and second control circuit can apply different voltage levels and timing parameters to compensate for signal delay, ensuring consistent display quality across the entire gate line while using simple GOA drive architecture.
2Device complexity
If single-sided GOA drive is adopted, then driver IC requirements are reduced, but far-terminal signal overcharging occurs leading to pixel voltage differences
Solution Approach 1:
The gate line control is segmented into two independent control circuits, each managing one terminal. This segmentation allows precise control of voltage signals at each terminal, preventing signal overcharging and pixel voltage differences while keeping the overall driver IC requirements low through the use of simple GOA drive transistors.
Solution Approach 2:
The patent implements a feedback mechanism where the first control circuit and second control circuit monitor and adjust voltage signals applied to the gate line terminals. This feedback ensures that voltage levels remain within optimal ranges, preventing overcharging and maintaining signal stability without requiring complex driver ICs.
3Ease of manufacture
If single-sided GOA drive is adopted, then manufacturing simplicity is improved, but signal delay causes far-terminal signal overcharging
Solution Approach 1:
The gate line is segmented into two controlled sections with separate control circuits. This segmentation allows each control circuit to independently manage voltage application timing and levels, preventing signal overcharging at the far terminal while maintaining the manufacturing simplicity of GOA drive architecture.
Solution Approach 2:
The control circuits are designed to apply voltage signals in a predetermined sequence and timing pattern. The first control circuit and second control circuit coordinate their voltage application timing in advance, ensuring that signals reach the far terminal before overcharging can occur, thereby eliminating the harmful effect while keeping the structure simple.
Data Source
AI summary
A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.