Display Driver IC Address Mapping for Non-Power-of-Two GRAM Arrays
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Solution Overview
Problem
The array depth and width of graphic random access memory (GRAM) in display driver integrated circuits are limited to powers of 2, leading to poor adaptability and inefficiencies in capacity and size, which cannot meet diverse requirements.
Innovation Solution
Incorporating an address mapper to map discontiguous addresses of memory arrays into contiguous addresses, allowing for array depths and widths that are not restricted to powers of 2, along with flexible customization of memory array capacities and sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the array depth of GRAM is limited to 2n, then the memory structure is simplified and easier to implement, but the array depth adaptation is limited and cannot meet different requirements
Solution Approach 1:
The patent divides the GRAM into multiple memory arrays (first memory array, second memory array, etc.) with different array depths. Each memory array can be independently configured with specific depth values, allowing the system to achieve flexible array depth adaptation without requiring the entire memory structure to conform to a single 2n depth constraint. This segmentation enables different depth requirements to be met by selecting appropriate memory arrays while maintaining overall structural manageability.
2Adaptability or versatility
If the array width of GRAM is limited to 2n bits, then the memory structure is simplified, but the array width adaptation is limited and cannot meet different requirements
Solution Approach 1:
The patent segments the GRAM into multiple memory arrays with different array widths (e.g., first memory array with 96 bits, second memory array with 192 bits). Each memory array can be independently designed with optimal width for specific applications, enabling the system to adapt to different width requirements by selecting or combining appropriate arrays. This eliminates the need for a single 2n-bit width constraint across the entire memory structure.
3Adaptability or versatility
If multiple memory arrays with different capacities are used, then the capacity can be flexibly set according to requirements, but the addresses of memory arrays become discontiguous
Solution Approach 1:
The patent introduces an address mapper as an intermediary component between the memory arrays and the address port. The address mapper receives discontiguous addresses from multiple memory arrays with different capacities and transforms them into contiguous address sequences. This mediator ensures that despite having memory arrays with varying capacities (e.g., 6400, 12800, 19200), the system presents a unified contiguous address space, simplifying memory access operations and data management while maintaining the flexibility to configure different capacities according to requirements.
4Area of stationary object
If the number of memory arrays is reduced, then the overall area is reduced and costs are lowered, but the capacity may not be sufficient to meet requirements
Solution Approach 1:
The patent applies local quality by configuring different memory arrays with different capacities and depths according to specific functional requirements. Instead of using uniform memory arrays throughout, the system selectively allocates resources - for example, using a first memory array with capacity 6400 for certain functions and a second memory array with capacity 12800 for other functions. This localized optimization allows the system to meet total capacity requirements while minimizing the overall number of memory arrays and reducing the total area occupied, thereby lowering costs.
Data Source
AI summary
A display driver integrated circuit and an electronic device are disclosed, and relate to the field of display technologies, to resolve a problem of poor array depth adaptation of a graphic random access memory. The display driver integrated circuit includes the graphic random access memory, where the graphic random access memory includes a plurality of memory arrays, an array depth of the memory array is not equal to 2n, and n is a positive integer, and an address mapper, coupled to an address port of the graphic random access memory, and configured to map addresses of the plurality of memory arrays, to make the addresses of the plurality of memory arrays to be contiguous.