Display Driver Circuit Hole Border Routing
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Solution Overview
Problem
Conventional display designs with holes or inactive regions in the active area face challenges in routing data and gate lines, leading to increased border width and congestion, which affects the efficiency and aesthetics of electronic devices.
Innovation Solution
The implementation of a display driver circuit that merges and splits control signals across multiple rows of pixels around inactive regions, using dummy circuits to balance parasitic loading, and routing lines in a way that minimizes congestion by extending them into the hole border region or keeping them within the active area, thereby reducing the minimum hole border envelope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data lines and gate lines are routed in a regular grid-like pattern across the display, then the routing is straightforward and simple, but the design cannot accommodate holes or inactive regions in the active area
Solution Approach 1:
The display active area is segmented into multiple regions by introducing holes or inactive regions, and the routing is divided into separate paths that go around these regions. This allows the display to accommodate non-standard active area designs while maintaining organized routing structures.
Solution Approach 2:
The routing approach transitions from a two-dimensional grid pattern to a three-dimensional routing strategy that goes around holes in the active area. By routing lines along the periphery of holes rather than through them, the design accommodates complex active area shapes without excessive congestion.
2Adaptability or versatility
If data lines and gate lines are routed around holes in the active area, then the display can accommodate inactive regions, but the border width increases due to congestion
Solution Approach 1:
Holes in the active area are designed with rounded or curved boundaries rather than sharp corners. This curvature allows routing lines to follow smooth paths around the holes, reducing congestion at corners and minimizing the border width required around inactive regions.
Solution Approach 2:
The routing strategy employs asymmetric routing patterns that adapt to the specific location and shape of holes in the active area. Rather than applying a uniform border width around all holes, the routing is optimized locally to minimize the impact on active area size while accommodating each hole's unique geometry.
3Productivity
If multiple row control lines are merged into a single segment routed by an inactive region, then the routing efficiency improves, but the parasitic loading increases
Solution Approach 1:
Multiple row control lines that would otherwise require separate routing paths are merged into a single shared segment that routes around inactive regions. This consolidation improves routing efficiency by reducing the number of separate connections needed, while the merged segment is designed to minimize parasitic effects.
Solution Approach 2:
Dummy circuits are introduced as intermediary elements connected to the merged control line segments. These dummy circuits provide additional parasitic loading that compensates for the reduced loading from merged lines, thereby balancing the electrical characteristics and maintaining signal integrity across all pixel rows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the border width around holes, increasing the active area size and improving the routing efficiency, allowing for more flexible and efficient display designs even with non-standard active areas.
Implementation Method 1
The display driver circuit is configured to output a control signal onto a first row control line coupled to a first row of the display pixels and to output the control signal onto a second row control line coupled to a second row of the display pixels, where the first and second row control lines are merged into a segment that is routed by the inactive region
Implementation Method 2
If desired, a dummy circuit such as a capacitor circuit may be coupled to the merged segment and may be configured to increase the parasitic on the first and second row control lines
Data Source
AI summary
An electronic device may include a display having display pixels formed in an active area of the display. The display further includes display driver circuitry for driving gate lines that are routed across the display. A hole such as a through hole, optical window, or other inactive region may be formed within the active area of the display. Multiple gate lines carrying the same signal may be merged together prior to being routed around the hole to help minimize the routing line congestion around the border of the hole. Dummy circuits may be coupled to the merged segment portion to help increase the parasitic loading on the merged segments. The hole may have a tapered shape to help maximize the size of the active area. The hole may have an asymmetric shape to accommodate multiple sub-display sensor components.