Display Driver Level Shifting Circuit for Power Reduction
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Solution Overview
Problem
Existing display device drivers consume high power due to the need for high gate voltages in both the input signals and internal nodes, which leads to inefficiencies in power management.
Innovation Solution
The driver incorporates a level shifting output circuit that elevates the high gate voltage of internal nodes, allowing the input signals and internal nodes to operate at a lower first high gate voltage while outputting a higher second high gate voltage, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the driver operates with high gate voltage in both input signals and internal nodes, then the output signal can maintain the required voltage level, but power consumption increases
Solution Approach 1:
The driver is divided into multiple stages, with only the final stage containing the level shifting output circuit that generates the high voltage output signal. Previous stages operate at lower voltages, segmenting the power consumption across different functional blocks and reducing overall energy usage while maintaining output requirements.
Solution Approach 2:
The level shifting output circuit dynamically changes the voltage parameter from a first high gate voltage in internal nodes to a second high gate voltage for the output signal. This parameter transformation allows internal circuitry to operate at lower voltages while still producing the required high voltage output, directly resolving the power consumption contradiction.
2Use of energy by moving object
If the clock signal toggles between low gate voltage and first high gate voltage, then power consumption is reduced, but the output signal still requires a higher second high gate voltage
Solution Approach 1:
The level shifting output circuit acts as an intermediary between the low-voltage internal nodes and the high-voltage output requirement. It receives the first high gate voltage from internal nodes and transforms it into the second high gate voltage for the output signal, mediating the voltage level transition without requiring the entire driver to operate at high voltage.
Solution Approach 2:
The level shifting output circuit performs parameter transformation by converting the voltage level from the first high gate voltage to the second high gate voltage. This allows the clock signal and internal nodes to operate at lower voltages for reduced power consumption while still achieving the required output voltage through controlled parameter change.
Data Source
AI summary
A driver including multiple stages is disclosed. At least one of the stages includes an input circuit configured to transfer an input signal to a first node in response to a clock signal, a first transistor connected between the first node and a second node, a carry circuit configured to output a carry signal having a first high gate voltage when the second node has the first high gate voltage, and a level shifting output circuit configured to output an output signal having a second high gate voltage higher than the first high gate voltage by level-shifting the first high gate voltage of the second node.