Display Panel Driver Layout for Narrow-Bezel Signal Routing
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Solution Overview
Problem
The existing display panels face challenges in reducing the bezel width due to the large space occupied by the peripheral driver circuit, which provides drive signals for pixel units.
Innovation Solution
The display panel design incorporates a driver circuit with a second power signal bus that partially overlaps the driver circuit, along with a first power signal bus and signal lines configured to minimize bezel area, and employs unilateral or bilateral driving methods to reduce bezel width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the peripheral driver circuit is configured to provide drive signals for pixel units, then the display panel can control pixel circuits, but the driver circuit occupies large space making it difficult to reduce bezel width
Solution Approach 1:
The patent transitions the driver circuit from a planar 2D layout to a 3D stacked configuration. Multiple driver circuits are arranged in different layers (first driver circuit in first layer, second driver circuit in second layer), utilizing the vertical dimension to reduce the horizontal footprint in the bezel region while maintaining full driving capability for pixel units.
Solution Approach 2:
The driver circuit functionality is segmented into multiple independent driver circuits distributed across different layers. Each driver circuit can independently provide drive signals to pixel units, allowing the system to maintain reliability while reducing the area occupied by any single driver circuit and the overall bezel region.
2Reliability
If multiple signal lines are routed through the bezel region to connect driver circuit and pixel circuit, then signal transmission is enabled, but the bezel width increases
Solution Approach 1:
Signal lines are routed through multiple layers vertically rather than horizontally across the bezel region. The first signal line group and second signal line group are disposed in different layers, with connection lines extending in the row direction and column direction through the stacked structure, reducing the horizontal space required in the bezel region.
Solution Approach 2:
Multiple signal lines are merged into a shared bus structure. The shared bus is disposed in the column direction and shared by multiple pixel circuits, reducing the total number of individual signal lines required and thereby reducing the bezel width while maintaining signal transmission capability.
Data Source
AI summary
Provided are a display panel and a display device. The display panel includes a driver circuit and a pixel circuit, a light-emitting element, and a first power signal bus and a second power signal bus. The light-emitting element includes a first electrode and a second electrode, a first power signal bus and a second power signal bus. The first power signal bus is connected to the pixel circuit, the pixel circuit is connected to the first electrode, and the second power signal bus is connected to the second electrode, and the second power signal bus at least partially overlaps the driver circuit. The first driver circuit is configured to provide a first control signal for the pixel circuit, and the first driver circuit includes a plurality of stages of first shift registers cascaded with each other in a first direction.