Display Data Driver Partitioning for Lower-Cost Panel Integration

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Solution Overview

Problem

Existing display devices face challenges in reducing manufacturing costs while maintaining efficient operation of the data and the data driver, and the data driver includes a shift register, a sampling latch, a holding latch, and a buffer configured to provide a data signal to the data line.

Innovation Solution

The integration of a sampling latch and a holding latch in a first chip different from the display panel, and the integration of a decoder and a buffer in the display panel, with the sampling latch in a first chip and the buffer in the display panel, and the integration of a level shifter between the sampling latch and the holding latch and the holding latch in the display panel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If all data driver components (sampling latch, holding latch, decoder, buffer) are integrated in a single chip, then device complexity is reduced, but manufacturing cost increases due to high voltage element requirements

Engineering Contradiction:
Improvedata driver integrationVSAvoidmanufacturing cost
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The data driver is segmented into two separate chips: a first chip containing low voltage elements (sampling latch, level shifter) and a second chip containing high voltage elements (holding latch, decoder, buffer). This segmentation allows each chip to be optimized for its specific voltage requirements, reducing overall manufacturing cost while maintaining functional integration.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If high voltage elements are integrated in the display panel, then manufacturing cost is reduced, but device complexity increases due to voltage level management

Engineering Contradiction:
Improvemanufacturing costVSAvoidvoltage level management
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

A level shifter is introduced as an intermediary component between the low voltage sampling latch and the high voltage holding latch/decoder/buffer. This level shifter manages the voltage level transitions, allowing high voltage elements to be integrated in the display panel while maintaining manageable device complexity through automated voltage level conversion.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If sampling latch and buffer are separated into different chips, then manufacturing cost is reduced, but device complexity increases due to inter-chip connections

Engineering Contradiction:
Improvemanufacturing costVSAvoidinter-chip connections
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The data driver is divided into two functional segments: a first chip containing the sampling latch and level shifter, and a second chip containing the holding latch, decoder, and buffer. This segmentation enables cost-effective manufacturing by allowing specialized processing for each chip type while the inter-chip connections are managed through standardized interfaces.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250391330A1Display device and electronic device including the same
Publication Date: 2025.12.25 SAMSUNG DISPLAY CO LTD
  • US20250391330A1 patent drawing
  • US20250391330A1 patent drawing
  • US20250391330A1 patent drawing

AI summary

A display device includes: a display panel including a pixel connected to a data line, the display panel being configured to display an image; and a data driver configured to provide a data signal to the data line, wherein the data driver includes: a shift register configured to generate a sampling signal; a sampling latch configured to latch image data in response to the sampling signal; a holding latch configured to store an output of the sampling latch; a decoder configured to convert an output of the holding latch into an analog signal; and a buffer configured to provide an output of the decoder to the data line, and wherein the sampling latch is integrated in a first chip different from the display panel, and wherein the buffer is integrated in the display panel.