Display Driver Parity Circuit for Error Detection
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Solution Overview
Problem
Existing display drivers face challenges with increased complexity and cost due to large chip areas and potential data errors in display memory, particularly when handling high-resolution displays, which can lead to erroneous data being written and displayed.
Innovation Solution
A display driver incorporating a parity generation circuit to generate parity data for display data, a parity check circuit for error detection, decoders, latch circuits, and data line driver sections to manage data lines, reducing the need for decoders in each data line driver section and enabling efficient data error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a calculation circuit is provided in each column driver to process display data, then the display panel can be driven, but the circuit becomes complicated and the chip area is increased
Solution Approach 1:
The calculation circuit is extracted from each column driver and relocated to a separate processor. The column drivers only retain the function of outputting data to data lines, significantly simplifying the driver circuit structure and reducing chip area while maintaining display panel driving capability
Solution Approach 2:
The processor performs multiple functions including calculation processing, parity generation, and data output control. This multi-functional approach eliminates the need for dedicated calculation circuits in each column driver, reducing overall circuit complexity
2Measurement precision
If the resolution of the display panel is increased, then the display quality is improved, but the amount of display data is increased and the driver circuit becomes complicated
Solution Approach 1:
The data processing burden is extracted from the driver circuit and transferred to the processor. The driver circuit only handles simple data output to data lines, while the processor performs calculation and parity generation. This separation allows the driver circuit to remain simple even as display resolution increases
Solution Approach 2:
The processor performs preliminary calculation and parity generation before data is sent to the display memory. This preliminary processing reduces the data processing burden on the driver circuit during high-resolution display operations
3Reliability
If parity check is performed for data error detection, then data reliability is improved, but the circuit area and design period are increased
Solution Approach 1:
The parity generation circuit and parity check circuit are merged into the processor. This integration eliminates the need for separate parity check hardware in the driver circuit, maintaining data error detection capability while minimizing additional circuit area
Solution Approach 2:
The processor performs self-service by generating and checking parity data internally. This self-contained approach eliminates the need for external parity check circuits, reducing overall device complexity while maintaining reliability
4Ease of operation
If voltage is applied to a word gate without expecting voltage, then the display memory can be accessed, but erroneous data may be written into the display memory
Solution Approach 1:
The processor generates parity data in advance before writing to the display memory. This preliminary parity generation allows the system to detect and prevent erroneous data writing even when voltage is unexpectedly applied to word gates
Solution Approach 2:
The parity check circuit provides feedback to detect data errors caused by unexpected voltage application. This feedback mechanism allows the system to identify and correct erroneous data writes, maintaining data integrity while preserving memory access capability
Data Source
AI summary
A display driver includes: a parity generation circuit which generates s-bit parity data for n-bit display data input through a processor interface, combines the n-bit display data and the s-bit parity data, and outputs the combined n-bit display data and s-bit parity data to a display memory as (n+s)-bit display data; a parity check circuit which performs data error detection for the (n+s)-bit display data sequentially input from the display memory in units of (n+s) bits, and outputs the n-bit display data; at least one decoder which decodes the n-bit display data output from the parity check circuit; a plurality of latch circuits which latch the data decoded by the decoder; and a plurality of data line driver sections which drive data lines of a display panel based on the data latched by the latch circuits.