Display Driver QB Node Discharge During Power-Off
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Solution Overview
Problem
In display devices, internal nodes (QB nodes) of gate and emission drivers remain at previous voltages during power-off sequences, leading to potential issues.
Innovation Solution
A driver design that includes a QB node discharging circuit to discharge QB nodes when high and low gate voltages are deactivated, utilizing transistors and capacitors to control and reset node voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If signals and voltages are deactivated during power-off sequence, then power consumption is reduced, but internal nodes retain previous voltages causing operational issues
Solution Approach 1:
The patent applies preliminary action by discharging the QB node before the power-off sequence is fully executed. The discharging circuit is activated in advance to clear residual voltages from internal nodes, ensuring that when power is completely cut off, no problematic voltage retention occurs. This preventive measure resolves the contradiction by maintaining reliability during power transition while still achieving power consumption reduction.
2Reliability
If QB node is discharged during power-off period, then voltage retention issues are prevented, but additional circuit components are required
Solution Approach 1:
The patent merges the QB node discharging function with existing power-off control circuits. The discharging circuit shares control signals and timing with the power-off sequence, and utilizes existing voltage lines and control logic. This integration approach achieves reliable QB node discharge without significantly increasing overall device complexity, as the new functionality is combined with existing infrastructure rather than added as a completely separate system.
Data Source
AI summary
A driver includes a plurality of stages. At least one stage includes: an input circuit configured to transfer an input signal to a Q node in response to a first clock signal, where the Q node includes a first Q node and a second Q node; a QB node controlling circuit configured to control a voltage of a QB node based on a voltage of the first Q node and a QB control signal; an output circuit configured to output an output signal, which has a high gate voltage, based on a voltage of the second Q node, and configured to output the output signal, which has a low gate voltage, based on the voltage of the QB node; and a QB node discharging circuit configured to discharge the QB node when the high gate voltage and the low gate voltage are deactivated.