Display Driver Reset Latch for Complete Clock Signal Reset
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Solution Overview
Problem
Conventional display panel architectures, particularly Tri-gate architecture, suffer from incomplete system resets due to trace differences, leading to inconsistent electromagnetic radiation and verification failures.
Innovation Solution
A driver with a reset latch module that latches the system reset signal for a predetermined period, ensuring complete output to clock signal output modules, thereby preventing overlap and inconsistent electromagnetic radiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If Tri-gate architecture is used to reduce the number of source driver chips, then the load of the source driver chip is reduced, but the charging capability becomes poor and reset becomes incomplete due to trace differences
Solution Approach 1:
The patent introduces a reset latch module that performs preliminary action by latching the reset signal before it is distributed to multiple clock signal output modules. This ensures that the reset signal is captured and held at a consistent state, preventing trace differences from causing inconsistent reset timing. The latch module proactively prepares the reset signal distribution, ensuring all modules receive the same reset state regardless of trace variations.
Solution Approach 2:
The reset latch module acts as an intermediary between the reset signal source and the multiple clock signal output modules. It mediates the reset signal distribution by receiving the reset signal, latching it to eliminate trace difference effects, and then distributing the latched signal to all modules. This intermediary function ensures uniform reset behavior across all modules despite physical trace variations.
2Device complexity
If reset signal is distributed directly without latching, then the device complexity is low, but electromagnetic radiation becomes inconsistent due to incomplete reset
Solution Approach 1:
The reset latch module performs preliminary action by latching the reset signal before distribution. This preliminary latching ensures that all clock signal output modules receive the reset signal at the same logical state, preventing inconsistent reset timing that would cause electromagnetic radiation issues. The latch proactively eliminates the problem before it manifests as electromagnetic interference.
Solution Approach 2:
The reset latch module serves as an intermediary that mediates between the reset signal source and multiple clock output modules. It captures the reset signal, holds it in a stable state, and then distributes it uniformly to all modules. This intermediary function ensures consistent reset timing across all modules, preventing the electromagnetic radiation inconsistencies that would otherwise occur due to trace differences.
3Manufacturing precision
If trace differences are not compensated, then the manufacturing precision requirement is low, but system reset becomes incomplete leading to verification failures
Solution Approach 1:
The reset latch module performs preliminary action by latching the reset signal before it is distributed to multiple modules. This preliminary latching compensates for trace differences by ensuring all modules receive the reset signal at the same logical state, regardless of physical trace variations. The latch proactively eliminates the need for high manufacturing precision in trace routing.
Solution Approach 2:
The reset latch module acts as an intermediary that compensates for trace differences. It receives the reset signal, latches it to eliminate the effects of trace variations, and then distributes the latched signal to all clock signal output modules. This intermediary function ensures consistent reset behavior across all modules without requiring high manufacturing precision in trace routing.
Data Source
AI summary
A driver and a display device are provided. The driver includes a reset latch module, a first clock signal output module, and a second clock signal output module. The reset latch module receives and latches a system reset signal to continuously output a reset signal for a predetermined period of time, so that the reset signal can be completely output to the first clock signal output module and the second clock signal output module.