Display Driver Semiconductor Device with Local Quality Gate Insulation
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Solution Overview
Problem
Conventional LCD source driver ICs face challenges in reducing chip size due to the larger size of high voltage transistors, which increases the overall chip size, especially since 70% of the driver IC is composed of high voltage transistors requiring thicker gate insulation layers and larger low-concentration drift regions.
Innovation Solution
The method involves forming trench isolating regions and well regions on a substrate, depositing chemical vapor deposition (CVD) and thermal oxide layers to create gate insulating layers of varying thicknesses, and patterning these layers to form high and low voltage semiconductor devices with optimized gate electrodes and source/drain regions, reducing the size of high voltage transistors and overall chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of gate insulation layer is increased for high voltage transistor, then the breakdown voltage of device is satisfied, but the size of transistor increases
Solution Approach 1:
The patent applies different gate insulation layer thicknesses to different transistor types on the same chip. High voltage transistors receive thicker gate insulation layers (first thickness) to satisfy breakdown voltage requirements, while low voltage transistors receive thinner gate insulation layers (second thickness) to minimize transistor size. This local differentiation resolves the contradiction by optimizing each transistor type for its specific voltage requirements rather than using a uniform thickness for all transistors.
2Reliability
If the size of high voltage transistor is increased, then the breakdown voltage requirement is met, but the chip size increases proportionally
Solution Approach 1:
The patent implements local quality by creating distinct processing regions for high voltage and low voltage transistors. High voltage transistor regions receive thicker gate insulation and larger drift regions to meet breakdown requirements, while low voltage transistor regions receive optimized thinner insulation and smaller dimensions. This allows the chip to accommodate high voltage transistors only where necessary, minimizing overall chip area while maintaining required breakdown voltage performance.
Solution Approach 2:
The patent segments the chip into multiple processing regions with different gate insulation thicknesses and transistor configurations. By dividing the chip into high voltage regions and low voltage regions, each with optimized parameters, the patent reduces the overall chip size compared to a uniform design where all transistors would require the larger dimensions needed for high voltage operation.
3Adaptability or versatility
If dual-gate oxidation method is used to implement transistor with two kinds of voltages, then high voltage and low voltage transistors are formed, but the overall chip size increases due to larger high voltage transistor size
Solution Approach 1:
The patent refines the dual-gate oxidation approach by applying local quality principles to each transistor region. Instead of using a single oxidation process for all transistors, the patent performs selective oxidation in different regions to create appropriate gate insulation thicknesses for high voltage and low voltage transistors separately. This allows low voltage transistors to maintain smaller sizes while high voltage transistors achieve required breakdown voltage, thereby reducing overall chip size compared to conventional dual-gate oxidation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the size of high voltage transistors, leading to a smaller chip size while maintaining optimal performance by using semiconductor devices suitable for each voltage level, thereby increasing the number of net dies and improving mis-matching characteristics and current efficiency.
Implementation Method 1
depositing a chemical vapor deposition (CVD) insulating layer through the first, second, and third regions of the substrate
Implementation Method 2
forming a first thermal oxide layer, a second thermal oxide layer, and a third thermal oxide layer on the first, second, and the third regions, respectively
Data Source
AI summary
A display driver semiconductor device includes a high voltage well region formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer formed using a deposition process. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer formed using a thermal process. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer.