Display Driver Semiconductor Device with Varying Gate Insulating Layers
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Solution Overview
Problem
Conventional LCD source driver ICs have a large chip size due to the size of high voltage transistors, which is exacerbated by the thickness of the gate oxide layer, leading to increased power consumption and reduced portability in high-definition displays.
Innovation Solution
A display driver semiconductor device manufacturing method that involves forming trench isolating regions, low-concentration drift regions, and varying gate insulating layers using chemical vapor deposition (CVD) and thermal oxide techniques to reduce the size of high voltage transistors, thereby minimizing the overall chip size while maintaining electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the gate oxide layer is increased to implement high voltage transistors, then the breakdown voltage capability is improved, but the transistor size increases proportionally
Solution Approach 1:
The patent applies different gate oxide layer configurations to different transistor types within the same chip. High voltage transistors receive thicker gate oxide layers (first gate insulating layer) while low voltage transistors receive thinner gate oxide layers (second gate insulating layer). This local differentiation allows each transistor type to have optimized electrical characteristics without unnecessarily increasing the size of all transistors on the chip.
Solution Approach 2:
The patent segments the gate insulating layer formation process into distinct stages and regions. The first gate insulating layer is formed selectively in high voltage transistor regions, while the second gate insulating layer is formed in low voltage transistor regions. This segmentation enables independent optimization of gate oxide thickness for different voltage requirements, resolving the contradiction between voltage capability and device size.
2Reliability
If the size of high voltage transistors is increased to satisfy breakdown voltage requirements, then the voltage endurance is improved, but the overall chip size increases
Solution Approach 1:
The patent implements local quality by providing enhanced gate insulation (thicker first gate insulating layer) only where high voltage endurance is required, rather than uniformly across the entire chip. This allows high voltage transistors to achieve the necessary voltage endurance while low voltage transistors maintain compact dimensions, thereby controlling the overall chip size.
Solution Approach 2:
The patent changes the gate oxide thickness parameter selectively based on transistor type. High voltage transistors utilize a larger gate oxide thickness parameter (first gate insulating layer) to achieve voltage endurance, while low voltage transistors use a smaller thickness parameter (second gate insulating layer) to minimize size. This parameter differentiation resolves the contradiction between voltage endurance and chip area.
3Adaptability or versatility
If dual-gate oxidation is used to implement transistors with two kinds of voltages, then the voltage versatility is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the gate insulating layer structure into two distinct layers formed through separate processing steps. The first gate insulating layer is formed by thermal oxidation in a first region, and the second gate insulating layer is formed by thermal oxidation in a second region. This segmentation of the manufacturing process enables precise control over gate oxide thickness for different voltage requirements while maintaining a systematic and manageable fabrication workflow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the size of the display driver IC, enhancing portability and power efficiency by optimizing the gate insulating layers and transistor structure, allowing for smaller, more efficient high-definition displays.
Implementation Method 1
depositing a chemical vapor deposition (CVD) insulating layer through the first, second, and third regions of the substrate
Implementation Method 2
forming a first thermal oxide layer, a second thermal oxide layer, and a third thermal oxide layer on the first, second, and the third regions, respectively
Data Source
AI summary
A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.