Display Driver Shift Register Timing Control
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Solution Overview
Problem
Display drivers face challenges in adapting to various display device specifications due to manufacturing variations and environmental temperature changes, leading to noise generation from steep and simultaneous current changes in source lines.
Innovation Solution
A display driver configuration that includes first to N-th latches capturing pixel data in synchronization with capture clock signals of different edge timings, and an N-stage shift register that shifts a load signal synchronized with a horizontal synchronizing signal, using flip-flops connected in series to supply outputs to the latches as capture clock signals, allowing for adaptable pixel drive voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a delay circuit using inverter elements is used to shift capture timing, then noise generation is suppressed by avoiding steep and simultaneous current changes, but the delay amount is fixed in advance and changed by manufacturing variations and environmental temperature, making it difficult to adapt to various display device specifications
Solution Approach 1:
The patent applies the dynamics principle by making the delay amount adjustable rather than fixed. The delay circuit is configured to allow adjustment of the delay amount according to display device specifications, enabling the system to adapt dynamically to different operating conditions while maintaining noise suppression through controlled timing shifts.
Solution Approach 2:
The patent implements parameter changes by allowing the delay amount to be varied based on manufacturing variations and environmental temperature. The delay circuit can adjust the timing shift parameter to compensate for these changes, ensuring consistent performance across different display devices and operating conditions while preventing simultaneous current changes that cause noise.
2Device complexity
If a fixed delay circuit is used, then the structure is simple, but the delay amount cannot be adjusted for different display device specifications
Solution Approach 1:
The patent transforms the static delay circuit into a dynamic one that can adjust its delay amount. This allows the circuit to adapt to different display device specifications without requiring a completely complex redesign, achieving versatility through controlled adjustability while maintaining reasonable structural simplicity.
Data Source
AI summary
First to N-th latches capture N pieces of pixel data indicative of the luminance levels of respective pixels in synchronization with first to N-th capture clock signals each having different edge timing. Voltages corresponding to the pieces of pixel data output from the first to N-th latches are applied to each of the data lines of the display device. In this case, first to N-th flip-flops formed in an N-stage shift register capture a single pulse load signal which is synchronized with a horizontal synchronizing signal in a video signal while sequentially shifting the load signal to subsequent stages in synchronization with a reference timing signal supplied from the outside. Outputs of the first to N-th flip-flops in the N-stage shift register are supplied as first to N-th capture clock signals, to the first to N-th latches, respectively.