Display Driver Sync Circuit Noise Immunity
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Solution Overview
Problem
Noise interference can cause failure in vertical and horizontal synchronization in display drivers, leading to image disturbances in display devices, especially when dedicated signal lines are affected.
Innovation Solution
A display driver with a sync extraction circuit, timing generator, and drive circuit that generates internal sync signals based on external sync period start instructions and asserts these signals even if external sync packets are not successfully received, ensuring synchronization and reducing image disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated signal lines are used for vertical and horizontal sync signals, then synchronization reliability is improved, but the number of signal lines increases
Solution Approach 1:
The patent introduces a data interface as an intermediary to transmit sync information. Instead of using dedicated signal lines, the sync packets are embedded within data transmission channels, allowing the data interface to mediate between the need for synchronization and the desire to reduce signal line count.
Solution Approach 2:
The patent combines sync signal transmission with data transmission by embedding sync packets within the data interface communication stream. This merging eliminates the need for separate dedicated signal lines for vertical and horizontal synchronization, reducing overall system complexity.
2Device complexity
If sync packets are transmitted through data interface, then the number of signal lines is reduced, but synchronization reliability deteriorates due to noise interference
Solution Approach 1:
The timing generator asserts internal sync signals at predetermined timing based on expected sync packet reception times, even before actual packets are received. This preliminary action ensures that synchronization is maintained proactively, preventing image disturbances that would occur if waiting passively for potentially noisy packet transmissions.
Solution Approach 2:
The system monitors the reception status of sync packets and adjusts internal sync signal assertion accordingly. When sync packets are successfully received, internal signals are asserted in response; when reception fails due to noise, the predetermined timing mechanism provides feedback-based compensation to maintain synchronization.
3Measurement precision
If internal sync signals are asserted in response to sync packets, then synchronization accuracy is improved, but image disturbances occur when packet reception fails
Solution Approach 1:
The timing generator is configured to assert internal sync signals at predetermined timing intervals that correspond to expected sync packet reception times. This preliminary assertion of sync signals ensures continuous synchronization without gaps, preventing image disturbances that would occur if sync signals were only asserted reactively upon successful packet reception.
Solution Approach 2:
The system prepares and asserts internal sync signals in advance based on predetermined timing, creating a cushion against potential packet reception failures. This prior cushioning ensures that even if noise causes packet loss, the synchronization rhythm is already established and image disturbances are prevented.
Data Source
AI summary
A display driver for a display device including a sync extraction circuit configured to generate a vertical sync source signal in response to a vertical sync period start instruction indicating a start of a vertical sync period, a timing generator configured to generate an internal vertical sync signal in response to the vertical sync source signal; and a drive circuit configured to drive the display panel in synchronization with the internal vertical sync signal.