Display Driver Time-Division Multiplexing for Lower Circuit Scale
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Solution Overview
Problem
Existing display drivers for high-definition liquid crystal or organic electroluminescence (EL) display devices face challenges with increased circuit scale and current consumption due to the rise in data lines, leading to potential power supply voltage drops and operation malfunctions.
Innovation Solution
A display driver that employs time division multiplexing to reduce the number of level shifters and DA converters by using a demultiplexer to distribute a single drive signal to multiple data lines, incorporating a first multiplexer, level shift part, digital analog conversion part, and output amplifier to generate and amplify gradation voltages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of data lines is increased for high-definition display, then the display resolution is improved, but the circuit scale of the display driver increases
Solution Approach 1:
The display driver is divided into multiple circuit blocks, where each circuit block processes pixel data for a specific group of data lines. This segmentation allows the driver to handle high-definition resolutions by distributing the processing load across multiple independent blocks, thereby managing circuit scale effectively while supporting increased display resolution
Solution Approach 2:
The display driver employs time division multiplexing to sequentially supply drive signals to different data lines in periodic time slots. This periodic action allows a reduced number of output amplifiers to drive multiple data lines by time-sharing their output, thus reducing circuit scale while maintaining high-definition display capability
2Productivity
If the number of level shifters and DA converters is increased to match the number of data lines, then the signal processing capability is improved, but the current consumption increases
Solution Approach 1:
Multiple pixel data processing functions are merged into shared level shifters and DA converters within circuit blocks. Instead of providing dedicated level shifters and DA converters for each data line, the invention combines these functions so that a reduced number of converters serve multiple data lines through time division multiplexing, thereby reducing current consumption while maintaining signal processing capability
Solution Approach 2:
The level shifters and DA converters are designed with multi-functionality to handle pixel data for multiple different data lines sequentially. Each converter in a circuit block can process data for different output lines at different time slots, making these components universal rather than dedicated, which reduces the total number of converters needed and thus lowers current consumption
3Adaptability or versatility
If the number of output amplifiers is increased to match the number of data lines, then the drive signal capability is improved, but the circuit scale increases
Solution Approach 1:
The output amplifiers operate in periodic time division mode, where each amplifier sequentially drives different data lines in alternating time slots. This periodic action enables a single amplifier to replace multiple amplifiers by time-sharing the drive signal output, significantly reducing the number of amplifiers needed and thus reducing circuit scale while maintaining the capability to drive all data lines
Solution Approach 2:
The system dynamically switches the connection between output amplifiers and data lines through demultiplexers controlled by timing signals. This dynamic reconfiguration allows the same amplifier to be connected to different data lines at different times, providing adaptable drive signal capability with a reduced number of amplifiers, thereby reducing circuit scale
Data Source
AI summary
A display driver and a display device including the same include multiple circuit blocks, each of which generates a signal representing, through time division multiplexing, voltage values corresponding to brightness levels indicated by respective K pixel data pieces as a drive signal, and generates first to Qth pixel data signals representing the K pixel data pieces with Q signals by time division multiplexing at least one pair of pixel data pieces consisting of two data pieces from among the K pixel data pieces. Each of the circuit blocks converts the first to Qth pixel data signals into first to Qth gradation voltages, for each of horizontal scanning periods, generates a gradation voltage signal representing, through time division multiplexing, voltage values corresponding to the respective K pixel data pieces expressed by the first to Qth gradation voltages, and outputs a signal amplified from the gradation voltage signal as the drive signal.