Display Driver Circuit Timing for Lower Signal Delay and Distortion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices face challenges in reducing signal distortion, signal delay, transistor degradation, and increasing channel width, which affect display quality and cost efficiency.
Innovation Solution
A semiconductor device with a driver circuit comprising multiple transistors and signal lines, where clock signals with different duty ratios are used to control transistor potentials, reducing signal delay and transistor degradation, and optimizing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the channel width of a transistor is increased to reduce signal delay, then signal delay is reduced, but the layout area increases
Solution Approach 1:
The driver circuit is divided into multiple stages (first driver circuit, second driver circuit, third driver circuit) with each stage having its own transistors and signal lines. This segmentation allows optimized signal paths that reduce delay without requiring excessive channel width in any single transistor, thereby controlling overall layout area.
Solution Approach 2:
The patent introduces a multi-dimensional signal transmission approach by using multiple signal lines (first signal line, second signal line, third signal line) and multiple clock phases (first clock signal, second clock signal) to transmit signals through different paths simultaneously, effectively reducing signal delay without increasing transistor channel width.
2Manufacturing precision
If the channel width of a transistor is increased to improve display quality, then display quality is improved, but the layout area and cost increase
Solution Approach 1:
The driver circuit is segmented into multiple stages (first driver circuit, second driver circuit, third driver circuit) with each stage having its own transistors and signal lines. This segmentation allows optimized signal paths that reduce delay without requiring excessive channel width in any single transistor, thereby controlling overall layout area.
Solution Approach 2:
The patent introduces a multi-dimensional signal transmission approach by using multiple signal lines (first signal line, second signal line, third signal line) and multiple clock phases (first clock signal, second clock signal) to transmit signals through different paths simultaneously, effectively reducing signal delay without increasing transistor channel width.
3Loss of information
If clock signals with different duty ratios are used to control transistor potentials, then signal distortion is reduced, but the device complexity increases
Solution Approach 1:
The patent uses periodic clock signals with different duty ratios (first clock signal and second clock signal) to control the switching of transistors in different driver circuit stages. This periodic control with varying duty cycles enables precise timing management that reduces signal distortion and ensures proper signal transmission through each stage of the driver circuit.
Data Source
AI summary
One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.