Display Data Driver Timing to Reduce Dynamic Current Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices experience issues with dynamic current consumption and de-sense phenomena due to noise interference, leading to reduced communication performance.
Innovation Solution
A display device with a data driver that includes a latch unit synchronized with a delayed latch clock signal and a switching control signal, synchronized with a horizontal synchronization signal, to manage data voltage output to pixels, reducing unnecessary dynamic current and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data voltages are continuously output to data lines without synchronized switching control, then pixels can be updated without delay, but unnecessary dynamic current increases and noise-induced de-sense phenomena occur
Solution Approach 1:
The patent applies periodic action by generating switching control signals synchronized with the latch clock signal, which is itself derived from the horizontal synchronization signal. This periodic switching control ensures data voltages are output only at appropriate intervals, reducing unnecessary dynamic current consumption while maintaining proper pixel updates and preventing noise-induced de-sense phenomena.
Solution Approach 2:
The patent implements preliminary action by generating the latch clock signal with a predetermined delay from the horizontal synchronization signal. This delayed latch clock signal then controls the switching control signal generation, ensuring that data voltages are output at the optimal moment before noise interference occurs, thereby improving communication performance while reducing energy waste.
2Reliability
If data voltages are output without synchronized switching control signals, then pixel update timing is simplified, but noise interference causes de-sense phenomena that deteriorate communication performance
Solution Approach 1:
The patent uses the latch clock signal as an intermediary between the horizontal synchronization signal and the switching control signal. This intermediary signal with predetermined delay coordinates the output timing of data voltages, ensuring synchronization without requiring complex direct coordination between multiple signals, thus improving reliability while managing complexity.
3Reliability
If latch clock signal is not delayed from horizontal synchronization signal, then signal generation is simpler, but unnecessary dynamic current increases and communication performance deteriorates
Solution Approach 1:
The patent applies parameter changes by introducing a predetermined delay parameter to the latch clock signal relative to the horizontal synchronization signal. This parameter adjustment optimizes the timing of data voltage output, reducing dynamic current consumption and preventing de-sense phenomena while maintaining manageable system complexity through a simple delay mechanism.
Data Source
AI summary
An embodiment of the present disclosure provides a display device including: a display panel including pixels; and a data driver connected to the pixels through data lines, wherein the data driver includes a latch unit that receives first image data synchronized with a horizontal synchronization signal and outputs the first image data in response to a first latch clock signal generated at a time that is delayed from a signal at which the horizontal synchronization signal is generated; a digital-to-analog converting unit that generates data voltages corresponding to the first image data using gamma voltages; and an output buffering unit that outputs the data voltages corresponding to the first image data to some of the data lines in response to a first switching control signal generated at a time that is delayed from a time at which the horizontal synchronization signal is generated.