Display Driver Timing Control for Electro-Optical Panel
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Solution Overview
Problem
In phase expansion driving of electro-optical panels, the delay of the enable signal differs between the left and right ends, leading to uneven driving times and potential display quality issues due to the short output period of the data signal and significant influence of enable signal delay, especially with increasing pixel density.
Innovation Solution
A display driver with a control circuit that adjusts the relative time relationships between the active period of the enable signal and the output period of the data signal in each sampling section, allowing for differential timing adjustments to synchronize the sampling operations across the panel, using a measuring circuit to measure potential changes and set appropriate time relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If phase expansion driving is used to drive many source lines simultaneously, then productivity is improved, but the relative timing between enable signal and data signal deteriorates due to signal delay
Solution Approach 1:
The patent applies local quality by making the timing relationship between the enable signal and data signal different for each sampling section. Specifically, the control circuit adjusts the timing so that the enable signal leads the data signal by a different amount in different sampling sections, compensating for the varying signal propagation delays across the panel. This allows each sampling section to have optimized timing despite the overall high-speed driving requirement.
2Manufacturing precision
If the number of pixels is increased to improve resolution, then manufacturing precision is improved, but the output period of data signal becomes excessively short, making timing control difficult
Solution Approach 1:
The patent applies dynamics by making the timing relationship adaptive rather than fixed. The control circuit dynamically adjusts the timing offset between the enable signal and data signal for each sampling section based on the specific requirements of that section. This dynamic adjustment allows the system to maintain appropriate timing margins even as the overall output period becomes excessively short due to high pixel density.
3Loss of time
If resistance and capacitance are added to control enable signal delay overall, then the delay time is controlled, but the relative timing in respective sampling sections cannot be controlled
Solution Approach 1:
The patent applies segmentation by controlling the timing relationship independently for each sampling section rather than applying a uniform delay control approach. The control circuit is configured to set different timing relationships for different sampling sections, allowing precise control of the relative timing between enable signal and data signal at each specific location across the panel.
Data Source
AI summary
A display driver includes a driving circuit and a control circuit. An electro-optical panel includes plural sampling sections respectively provided for a predetermined number of plural source lines. The control circuit causes a relative time relationship between an ith graded output period of the driving circuit and an ith active period of an enable signal when a sampling operation is enabled for the ith sampling section to differ from a relative time relationship between a jth graded output period of the driving circuit and a jth active period of the enable signal when the sampling operation is enabled for the jth sampling section.