Display Driver DAC Architecture for Faster Pixel Voltage Settling
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Solution Overview
Problem
Existing display drivers face challenges in shortening the settling time of the voltage follower input, which hinders the ability to drive pixels at high speed within a short period, particularly when using D/A conversion methods with resistor strings and switching arrays.
Innovation Solution
The display driver incorporates a configuration with two binary-weighting D/A conversion circuits connected in series, where the resistance values of the first and second variable resistance circuits are set based on upper and lower bit data of the display data, respectively, to enhance driving speed and reduce circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a resistor string and switching array are used for D/A conversion, then the circuit can generate multiple voltages, but the settling time of the voltage follower input becomes too long
Solution Approach 1:
The patent divides the single D/A conversion process into two sequential stages: first converting upper bit data to voltage, then converting lower bit data and adding it to the first voltage. This segmentation allows each conversion stage to operate independently with optimized settling time, solving the contradiction between accurate multi-voltage generation and fast settling.
Solution Approach 2:
The first D/A conversion circuit performs preliminary conversion of the upper bit data to generate the first voltage before the second conversion occurs. This preliminary action establishes a base voltage that reduces the settling burden on the second conversion stage, enabling faster overall settling while maintaining precision.
2Productivity
If the driving period is shortened to increase frame rate, then the display speed increases, but the pixel driving time becomes insufficient
Solution Approach 1:
The pixel driving period is segmented into two phases: first pixel driving using the first voltage from upper bit conversion, then second pixel driving using the second voltage from lower bit conversion. This segmentation allows the total driving time to be distributed across two shorter intervals, enabling higher frame rates while ensuring sufficient driving time for each pixel update.
3Device complexity
If a ladder resistance circuit is used, then the circuit structure is simple, but the circuit size is large
Solution Approach 1:
The patent replaces the traditional ladder resistance circuit with two separate binary-weighted D/A conversion circuits that process upper and lower bits independently. This segmentation eliminates the need for a large-scale ladder structure while maintaining the required voltage generation capability, significantly reducing circuit size without oversimplifying the overall architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases driving speed by enabling current-driven electric potential generation and allows for appropriate gain settings based on driving polarity, effectively reducing the settling time and circuit size compared to traditional ladder resistance circuits.
Implementation Method 1
The settling time is the time for charging the input parasitic capacitance of the voltage follower from the resistor string via the switching array
Data Source
AI summary
A display driver includes an operational amplifier, a D/A conversion circuit, a resistance circuit, and a resistance element. The D/A conversion circuit includes first and second variable resistance circuits including one end to which first and second voltages are input and another end connected to an inverting input node. The resistance circuit is provided between the inverting input node and an output node. The resistor is provided between the output node and the inverting input node. A resistance value of the first variable resistance circuit is set based on upper bit data of display data. A resistance value of the second variable resistance circuit is set based on lower bit data of the display data.