Display Driving Apparatus Timing Control for EMI Reduction
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Solution Overview
Problem
Existing display driving apparatuses for plasma display panels (PDPs) face challenges in reducing electromagnetic interference (EMI) and power consumption, particularly in managing peak current and capacitive loads during data electrode driving.
Innovation Solution
A display driving apparatus that includes a change judgment unit, transition direction match judgment units, delay units, and a control unit to synchronize and delay drive signals for display output terminals, optimizing the timing of voltage changes and using a two-step voltage driving method to reduce peak current and EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a display driving apparatus drives multiple data electrodes simultaneously with voltage changes, then the display output is updated efficiently, but the peak current increases and EMI is generated
Solution Approach 1:
The patent segments the simultaneous voltage change operation into sequential operations by introducing timing control that divides data electrodes into groups. The driving operation is segmented across multiple time slots, where only a subset of electrodes undergo voltage changes at any given moment, thereby reducing peak current while maintaining overall display update efficiency
Solution Approach 2:
The patent implements periodic action by cycling through different groups of data electrodes in successive time periods. Each group undergoes voltage changes at scheduled intervals, creating a periodic driving pattern that distributes the current load over time rather than concentrating it in a single simultaneous operation
2Speed
If voltage levels are changed frequently to update display data, then the display refresh rate is maintained, but power consumption increases
Solution Approach 1:
The patent applies partial action by selectively updating only those data electrodes whose display data has actually changed, rather than refreshing all electrodes in every cycle. This selective updating approach maintains the necessary display refresh rate while significantly reducing the frequency of unnecessary voltage transitions and associated power consumption
Solution Approach 2:
The patent performs preliminary action by detecting voltage level changes and preparing timing control signals in advance before the actual voltage transition occurs. This advance preparation allows the system to coordinate voltage changes optimally, avoiding unnecessary frequent switching and reducing overall power consumption while maintaining display refresh performance
3Productivity
If all display output terminals change voltage simultaneously, then the display data is updated quickly, but capacitive charge imbalance occurs
Solution Approach 1:
The patent segments the simultaneous voltage change operation into sequential operations by introducing timing control that divides data electrodes into groups. The driving operation is segmented across multiple time slots, where only a subset of electrodes undergo voltage changes at any given moment, thereby reducing peak current while maintaining overall display update efficiency
Solution Approach 2:
The patent employs feedback mechanisms to monitor the voltage levels of data electrodes and adjust the timing control signals accordingly. By detecting the actual voltage states and using this information to coordinate subsequent voltage changes, the system maintains capacitive charge balance across electrodes while still achieving efficient display data updates
Data Source
AI summary
A display driving apparatus according to an implementation of the present invention includes: a first delay circuit that generates latch control signals changing with different timings; a second delay circuit that generates falling delay signals and rising delay signals by delaying the latch control signals; a delay selection circuit that (i) selects the falling delay signals or the rising delay signals when pixel data for adjacent display output terminals have changed in different directions and (ii) selects the latch control signals when pixel data for adjacent display output terminals have changed in the same direction; and a step control circuit that drives the display output terminals with timings of the signals selected by the delay signal circuit.