Image Display Driving Circuit Black Level Response Speed

The patent segments the data writing process into two distinct phases: a first data writing period for initial charge accumulation and a second data writing period for fine-tuning. This segmentation allows the system to use different current levels appropriately - higher current in the first phase to quickly charge the capacitor, then lower current in the second phase to adjust the final value, thereby achieving fast response without requiring continuously high current that would violate area constraints.

The patent implements periodic action by dividing the data writing operation into multiple time periods with different characteristics. The first data writing period uses a higher current level for rapid charging, while the second data writing period uses a lower current level for precise adjustment. This periodic variation in writing current allows the system to achieve both fast response speed and compliance with pixel area constraints.

The patent applies preliminary action by performing the majority of the charge accumulation during the first data writing period when higher current is available. The storage capacitor is quickly charged to near its target value during this initial phase, eliminating the need for a prolonged second phase. This preliminary charging action significantly reduces the total data writing time while maintaining black-level display accuracy.

The patent implements partial action by using excessive current during the first data writing period to rapidly charge the storage capacitor. Instead of using a moderate current throughout the entire writing period, the system temporarily applies higher current than strictly necessary, then reduces it during the second period for fine adjustment. This approach achieves accurate black-level display in less time by allowing temporary excessive action followed by correction.