Display Driving Circuit Embedded Clock EMI Reduction
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Solution Overview
Problem
Current display driving circuits face challenges in efficiently transmitting data signals with embedded clock signals, particularly in high-resolution displays, where electromagnetic interference (EMI) and clock data recovery are concerns, leading to instability and inefficiency.
Innovation Solution
The proposed display driving circuit includes a type detector, window generator, buffer, and multiplexer to process data packets with embedded clock signals, generating multiplexed reference clocks and extracting data signals using multi-phase clocks, while minimizing EMI through the use of first and second type data packets with distinct transition patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock embedded signaling is used to transmit data at high speed, then data transmission speed is improved, but electromagnetic interference increases
Solution Approach 1:
The data transmission is segmented into two types of data packets: first type packets transmit data during the high period of the embedded clock signal, while second type packets transmit data during the low period. This segmentation distributes the electromagnetic energy across different time slots, preventing concentration at a single frequency and thereby reducing EMI while maintaining high transmission speed.
Solution Approach 2:
The system employs periodic alternation between first type and second type data packets, with each type occupying different phases of the clock signal cycle. This periodic action ensures that electromagnetic energy is distributed across multiple frequency components rather than concentrated at one frequency, effectively reducing EMI while preserving high-speed data transmission capability.
2Productivity
If clock data recovery is implemented to recover clock and data, then data transmission efficiency is improved, but system complexity increases
Solution Approach 1:
A dedicated clock recovery circuit is introduced as an intermediary component that extracts and recovers the embedded clock signal from the data stream. This separate clock recovery mechanism simplifies the overall system architecture by providing a clean, recovered clock signal that can be used for synchronized data sampling, thereby improving transmission efficiency while managing complexity through functional separation.
3Object-generated harmful factors
If first type and second type data packets are used to reduce EMI, then electromagnetic interference is reduced, but device complexity increases
Solution Approach 1:
The system dynamically selects between first type and second type data packets based on real-time requirements. A type detector identifies the appropriate packet type, and a multiplexer switches between different transmission modes. This dynamic adaptability allows the system to reduce EMI by alternating packet types while maintaining operational flexibility, managing complexity through intelligent control rather than fixed architecture.
Data Source
AI summary
The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.