Display Driving Circuit Clock Synchronization for EMI Reduction
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Solution Overview
Problem
High-frequency internal clock signals in display driving circuits generate harmonics, leading to electromagnetic interference (EMI) and increased power consumption, particularly as display resolution increases.
Innovation Solution
A display driving circuit operates in synchronization with a relatively low-frequency internal clock signal, using a buffer controller to store and process pixel data across multiple buffers, with image processing units generating processed data that is delayed and provided to a source driver, which operates with a separate, lower-frequency clock signal, thereby reducing EMI and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the internal clock signal frequency is increased to display high-speed image signals, then the display speed and resolution are improved, but electromagnetic interference and power consumption increase due to generated harmonics
Solution Approach 1:
The patent divides the high-speed data transmission function into multiple parallel channels. Instead of using a single high-frequency clock signal, the system segments the pixel data into multiple groups and transmits them through separate data lines simultaneously, each synchronized with a lower-frequency clock signal. This segmentation allows the display to achieve high-speed performance without requiring a single high-frequency clock that would generate harmful harmonics.
Solution Approach 2:
The patent introduces an intermediate processing stage between the image signal input and the display output. This intermediate stage includes multiple image processing units that receive pixel data, process it in parallel, and prepare it for display. These intermediate units operate at lower frequencies and act as mediators that break down the high-speed transmission requirement into multiple lower-frequency operations, thereby reducing electromagnetic interference while maintaining overall display speed.
2Speed
If the internal clock signal frequency is increased to transmit high-speed image signals, then the image signal transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent segments the image signal transmission into multiple parallel data lines, each operating at a lower frequency. By dividing the total data transmission task across multiple lower-frequency channels, the system achieves the same overall transmission speed without requiring any single channel to operate at high frequency, thereby reducing the power consumption associated with high-frequency clock generation and signal switching.
Solution Approach 2:
The patent employs periodic action by using multiple data lines that transmit data in alternating cycles. Each data line operates periodically with a lower-frequency clock signal, and the combined effect of multiple periodic transmissions achieves the required overall data throughput. This periodic, multi-channel approach reduces instantaneous power consumption compared to continuous high-frequency operation on a single channel.
3Object-generated harmful factors
If multiple buffers and image processing units are used to operate with lower-frequency clock signals, then EMI and power consumption are reduced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing multiple image processing units that perform identical functions in parallel. Each processing unit is a universal module capable of handling pixel data independently, and these identical modules can be replicated and configured in different patterns to suit various display resolutions and requirements. This modular, universal design reduces overall system complexity compared to designing custom, non-reusable circuitry for each function.
Solution Approach 2:
The patent implements a nested structure where multiple image processing units are organized hierarchically. The processing units are grouped and controlled by a central buffer controller that coordinates their operation. This nested organization allows the complex multi-unit system to be managed through a hierarchical control structure, reducing the apparent complexity by providing a unified control interface while maintaining the parallel processing architecture that reduces EMI.
Data Source
AI summary
A display driving circuit includes first through (2*n)-th buffers, a buffer controller, first through n-th image processing units, and a source driver. The buffer controller circularly selects one of the first through (2*n)-th buffers in an order from the first buffer to the (2*n)-th buffer at each of a plurality of first time intervals, and stores pixel data received during the first time interval in the selected buffer. Each of the first through n-th image processing units is coupled to two corresponding buffers among the first through (2*n)-th buffers, and processes the pixel data, which are stored in at least one of their corresponding buffers, during n of the first time intervals to generate processed data when the pixel data are stored in the corresponding buffer during the first time interval. The source driver generates analog signals based on the processed data.