Display Driving Circuit Duration Control Latch
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Solution Overview
Problem
Existing electroluminescent display devices face challenges in efficiently controlling the light emitting duration of electroluminescent diodes, such as OLEDs, QLEDs, and Micro LEDs, which affects gray scale display and power consumption, especially at varying refresh frequencies.
Innovation Solution
A driving circuit comprising a first transistor, a duration control circuit, and a latch circuit, which allows independent control of the light emitting duration by providing a duration data signal to the transistor gate and latching the signal, enabling stable operation at both low and high refresh frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional driving circuit is used to drive electroluminescent diodes, then the light emitting device can be driven, but the light emitting duration cannot be precisely controlled, affecting gray scale display and power consumption
Solution Approach 1:
The driving circuit is segmented into functional modules: a duration control circuit that generates duration signals, a latch circuit that stores the duration signal, and a driving transistor that controls the light emitting device. This segmentation allows precise control of light emitting duration through the duration signal while maintaining modular circuit design.
Solution Approach 2:
The latch circuit preliminarily latches the duration signal from the duration control circuit before the light emitting device is driven. This preliminary action ensures that the duration signal is stable and ready, enabling precise control of the light emitting duration without requiring continuous signal adjustment during the emitting period.
2Manufacturing precision
If the light emitting duration is extended to improve gray scale display, then display quality improves, but power consumption increases
Solution Approach 1:
The driving circuit dynamically adjusts the light emitting duration by controlling the duration signal input to the latch circuit. This dynamic control allows the system to extend the emitting duration when higher gray scale quality is required while reducing the duration when power conservation is prioritized, adapting to different display scenarios in real-time.
Solution Approach 2:
The circuit changes the time parameter of the duration signal to control the light emitting duration. By varying this temporal parameter, the system achieves different gray scale levels without changing other critical parameters, thereby optimizing the balance between display quality and power consumption.
3Productivity
If refresh frequency is increased to improve display update speed, then display responsiveness improves, but signal stability deteriorates
Solution Approach 1:
The latch circuit performs preliminary latching of the duration signal before the light emitting period begins. This preliminary action ensures that even when refresh frequency is increased, the duration signal remains stable during the critical emitting period, as the latch circuit maintains the signal state without requiring continuous external input.
Solution Approach 2:
The latch circuit maintains the duration signal continuously during the light emitting period, ensuring uninterrupted and stable signal delivery. This continuous maintenance of the signal state allows the system to operate at high refresh frequencies while preserving signal stability throughout the entire emitting duration.
Data Source
AI summary
An embodiment of the present disclosure provides a driving circuit, a driving method thereof, a display panel and a display device. The driving circuit includes a first transistor electrically connected between a signal input terminal and a light emitting device to be driven, a duration control circuit configured to provide a signal of a duration data signal terminal to a gate of the first transistor in response to a signal of a duration scanning signal terminal, and a latch circuit electrically connected with the gate of the first transistor and configured to latch the signal of the gate of the first transistor.