Display Driving Circuit Enable Signal Synchronization
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Solution Overview
Problem
Existing display apparatuses face issues with power consumption due to variations in timing of scan signals generated by different level shift circuits, leading to inefficiencies in image display.
Innovation Solution
A method and circuit configuration where a common enable signal is used to synchronize the rising and falling timings of scan signals across all scan lines, reducing the capacitance load on the common transmission line and thereby decreasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a level shift circuit is provided for every scan line to generate scan signals, then the scan signals can be generated with appropriate amplitude for driving electro-optical devices, but the timing of scan signals generated by different level shift circuits varies due to circuit characteristic variations, causing image display problems
Solution Approach 1:
Multiple level shift circuits are merged into a single level shift circuit. The patent uses one level shift circuit to generate a reference signal, which is then distributed to multiple logic circuits (AND gates) that generate scan signals for different scan lines. This eliminates the need for separate level shift circuits for each scan line, ensuring timing consistency while reducing circuit complexity.
Solution Approach 2:
The function of generating scan signals is segmented between a single level shift circuit and multiple logic circuits. The level shift circuit generates a reference signal, and individual logic circuits (AND gates) generate scan signals for specific scan lines by combining the reference signal with enable signals. This segmentation allows timing synchronization while maintaining the ability to drive multiple scan lines.
2Reliability
If a common enable signal is used to synchronize scan signals across all scan lines, then timing consistency is improved, but the capacitance load on the common transmission line increases, leading to higher power consumption
Solution Approach 1:
The enable signal transmission is extracted and optimized by connecting it to a common transmission line that serves all logic circuits. This centralized approach allows for better control of the capacitance load and power consumption compared to having separate enable signal lines for each scan line.
Solution Approach 2:
The common transmission line serves as a universal channel for transmitting enable signals to multiple logic circuits simultaneously. This multi-functional approach reduces the total capacitance load compared to having dedicated enable signal lines for each scan line, thereby reducing power consumption while maintaining timing synchronization.
3Ease of operation
If logic circuits are electrically connected to the common transmission line during the entire horizontal scan period, then the enable signal can be transmitted to all logic circuits, but the total capacitance load on the transmission line increases, resulting in higher power consumption
Solution Approach 1:
The electrical connection between logic circuits and the common transmission line is made periodic rather than continuous. Each logic circuit is connected to the common transmission line only during the specific time period when it needs to receive the enable signal, which corresponds to the horizontal scan period for its associated scan line. This periodic connection reduces the total capacitance load and power consumption compared to continuous connection.
Solution Approach 2:
The electrical connection status of logic circuits to the common transmission line is made dynamic rather than static. The connection is established and disconnected at appropriate times during the horizontal scan period based on which scan line is currently being activated. This dynamic connection approach optimizes power consumption by minimizing the capacitance load on the transmission line at any given time.
Data Source
AI summary
A pixel selection control method, driving circuit, display apparatus and electronic instrument are disclosed. A driving circuit includes a logic circuit configured to receive a reference signal associated with a line of pixels. The reference signal has a first logic level or a second logic level. The driving circuit also includes a switch circuit configured to receive the reference signal and an enable signal, and to provide the enable signal to the logic circuit when the reference signal is at the first logic level. A display apparatus may be provided that includes the driving circuit.